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# Diamond as the heat spreader for the thermal dissipation of GaN-based electronic devices
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Liwen Sang
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To cite this article: Liwen Sang (2021) Diamond as the heat spreader for the thermal dissipation of GaN-based electronic devices, Functional Diamond, 1:1, 174-188, DOI: 10.1080/26941112.2021.1980356
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To link to this article: https://doi.org/10.1080/26941112.2021.1980356
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© 2021 The Author(s). Published by Informa UK Limited, trading as Taylor & Francis Group, on behalf of Zhengzhou Research Institute for Abrasives & Grinding Co., Ltd.
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Published online: 15 Oct 2021.
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Review
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# Diamond as the heat spreader for the thermal dissipation of GaN-based electronic devices
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Liwen Sanga,b
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a International Center for Materials Nanoarchitectonics (MANA ), National Institute for Materials Science (NIM S), Tsukuba, Ibaraki, Japan; bJST-PRESTO , The Japan Science and Technology Agency, Tokyo, Japan
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# ABSTRACT
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With the increasing power density and reduced size of the GaN-based electronic power converters, the heat dissipation in the devices becomes the key issue toward the real applications. Diamond, with the highest thermal conductivity among all the natural materials, is of the interest for integration with GaN to dissipate the generated heat from the channel of the AlGaN/ GaN high electron mobility transistors (HEMTs). Current techniques involve three strategies to fabricate the GaN-on-diamond wafers: bonding of GaN with diamond, epitaxial growth of diamond on GaN, and epitaxial growth of GaN on diamond. As a result of the large lattice mismatch and thermal mismatch, the integration of GaN-on-diamond wafer is suffered from stress, bow, crack, rough interfaces, and large thermal boundary resistance. The interfaces with transition or buffer layers impede the heat flow from the device channel and greatly influence the device performance. In this review, we summarize the three different techniques to achieve the GaN-on-diamond wafers for the fabrication of AlGaN/GaN HEMTs. The problems and challenges of each method are discussed. In addition, the effective thermal boundary resistance between GaN and diamond, which characterizes the heat concentration, is analyzed with regard to different integration and measurement methods.
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# ARTICLE HISTORY
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Received 13 June 2021
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Accepted 26 August 2021
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# KEYWORDS
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Semiconductor;
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Heat-related
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# 1. Introduction
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Benefitted from the high breakdown voltages (10 times higher than Si), high switching speed (over GHz), compact size, and tunable electronic architecture [1–7], III-V nitride semiconductor is becoming one of the best candidates for high-power electronics to enable the increasing power density and high conversion efficiency. The commercialized AlGaN/GaN high electron mobility transistors (HEMTs) have led to the entry into the mediumpower market, and play a central role for the RF and millimeter-wave applications [8–11]. In the applications of 5 G communications, radar, and electronic warfare, the HEMTs devices can offer more than 10 times higher power density than the existing Si technologies [12]. This giant power induces a huge amount of heat in the chip area, creating localized hot spots with fluxes above 10 kW/cm2 and package-level volumetric heat generation that can exceed 100 W/cm−3. The high-level power dissipation results in the challenges using conventional approaches for the thermal management. With the increased power density, self-heating inside the devices becomes an essential issue that accelerates the failure and poor reliability in the real application. Thermal
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dissipation through conventionally used approaches is no longer adequate. To achieve the effective thermal dissipation, the heat spreader with a much higher thermal conductivity is required.
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The current GaN wafers are typically grown on sapphie, silicon (Si), silicon carbide (SiC), or free-standing GaN substrates, whose thermal conductivities are 35, 150, 400, and 280 W/mK, respectively [13–15], which are far from the requirements. The ideal heat spreader would be a substrate that is both highly thermally conductive and electrically insulating. Diamond, with the thermal conductivity up to 2400 W/mK at room temperature for the single crystals, and approaching 2000 W/ mK for the polycrystals, is the best candidate as a heat spreader for GaN power transistors [16–19]. Early simulations and modelling showed that the passive thermal extraction by direct contact with diamond could dramatically reduce junction temperatures by 25-50% [20– 23]. However, as shown in Table 1, diamond and GaN exhibit widely mismatched properties, such as the crystalline structures, lattice constants and thermal expansion coefficients (TEC), making them challenging as bonded or growth pairs [24–28].
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Over the past twenty years, a variety of methods have been developed to utilize diamond as the heat spreader for AlGaN/GaN power transistors. The developed wafer is therefore called “GaN-on-diamond wafer”. The approaches are summarized in Figure 1, which include: (1) bonding of diamond to GaN wafers or directly to the HEMT devices with/without an adhesion layer, (2) GaN epitaxial growth on single-crystal or poly-crystal diamond substrate, then fabrication of HEMT devices, and (3) nanocrystalline or poly-crystalline diamond growth on the frontside or backside of GaN or the HEMTs devices. For the three approaches, the thermal resistance
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Table 1. T he lattice constant and thermal expansion coefficient of GaN, sapphire, Si and diamond at room temperature.
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<table><tr><td>Substrate</td><td>GaN (a-axis)</td><td>Sapphire</td><td>Si</td><td>Diamond</td></tr><tr><td>Lattice constant (Å)</td><td>3.189</td><td>4.758</td><td>5.420</td><td>3.567</td></tr><tr><td>TEC (×10-6K-1)</td><td>5.6</td><td>4.5-5.8</td><td>2.6</td><td>~1.1</td></tr></table>
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at the GaN/diamond, which is referred to the “effective thermal boundary resistance $( T B R _ { e f f } ) ^ { 3 }$ ”, is one of the factors that significantly increases the overall temperatures during device operation. Therefore, the optimizations on the integration technique and interface property are important. In this review, the state-of-the-art development on the GaN-on-diamond wafer and the modified fabrication process for HEMTs with regard to different integration methods will be presented. The strategies to improve the interfaces and reduce the $T B R _ { e f f }$ will be summarized and discussed. The device performances will be further shown with respect to different methods.
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# 2. Integration of the diamond to GaN or HEMTs through bonding technique
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The concept of harvesting the III-V epitaxial layers from one substrate and thermally bonding them to another
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(a) Top:GaN wafer bonding to diamond then fabricate HEMT devices; Bottom:HEMTsdevices directly bondingto diamond substrate
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(b） HEMT devices epitaxial grown on diamond substrate
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(c) Top:Diamond grown on the top of HEMTs devices; Bottom:Diamond epitaxially grown on HEMTwafers
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Figure 1. Fabrication of the GaN-on-diamond wafer for the HEMT devices. S: source, D: Drain, G: gate.
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substrate was proposed in the 1990s [29,30]. In 1997, Kelly et al. firstly demonstrated the lift-off of GaN film from sapphire substrate by illuminating the interface with a pulsed laser [31], which enabled the development of the GaN bonding technology. With the development of GaN-on-Si technology [32,33], the bonding process of GaN or HEMTs wafer became much easier due to the easy removal of the Si substrate. The advantage for the GaN bonding to diamond is that the crystal quality of both GaN and diamond can be guaranteed after the bonding.
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The formation of GaN-on-diamond wafer started with GaN or AlGaN/GaN HEMT epitaxial layers grown on a silicon substrate [34]. Other substrates, such as sapphire, silicon carbide, or aluminum nitride may also be used. In order to preserve the orientation of the epilayers, which is required to fabricate HEMTs on this structure, the epilayer was transferred twice (Figure 1 (a) top). The GaN-epilayer structure was firstly bonded to another sacrificial carrier. The growth substrate was then removed using either a wet chemical or dry etching process that is selective to GaN, leaving GaN epilayers flipped. An atomically flat dielectric layer was then deposited to bond with the diamond. The sacrificial carrier wafer was finally removed, leaving a composite wafer in which the GaN epilayers were attached to the diamond substrate. In this case, diamond was bonded to the N-polar HEMT devices. This process maintains the growth direction and the orientation of the built-in polarization fields of the GaN HEMTs for the realization of the 2D electron gas (2DEG). However, due to the bowing of the wafer, the optical lithography was unavailable for the process while an electron beam lithography was utilized for the device fabrication. Silicon nitride (SiN ), with a low thermal conductivity, was the typical adhesive dielectric layer, the heat barrier therefore was mainly located at the interface between GaN and diamond.
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Since the GaN used in this process can be grown on Si substrate, in principle, this process can be scaled to wafers of any size. But the wafer bow and wafer cracks resulted from different stresses during the formation of GaN-on-diamond wafer greatly limit the wafer size. Except for the lattice mismatch between the film and substrate, the thermal stress is also a well-known challenge. The thermal stresses arise due to the thermomechanical properties of the layers in the stack [35], the differences in the thermal expansion coefficients. The stresses bowed and/or warped the wafers as they cooled down from the process temperature to room temperature. By 2007, this process was improved and the 2-inch diameter GaN-on-diamond wafer was produced. In 2009, Francis et al. published the first demonstration of a 4-inch GaN-on-diamond wafer, as shown in Figure 2 [34, 36]. The interface between GaN and diamond through the adhesive layer was characterized by the acoustic properties using picosecond laser-ultrasonic probing. The measurement indicated a good adhesion
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of the interlayer to both GaN and diamond. The GaNon-diamond wafer technology has been demonstrated with 80 to 100 µm thick diamond substrates, which are mechanically stronger and flatter than that of the thin wafers. The developed GaN-on-diamond substrates were then utilized for the fabrication of devices, which demonstrated transition frequencies up to 85 GHz [37]. A comparison of device performances between GaNon-silicon and GaN-on-diamond was reported, which confirmed that the bonding process could avoid the damage to the active region of HEMTs [38]. The fabricated GaN HEMT-on-diamond transistor had a power density of 2.79 W/mm at 10 GHz. The device on SiC had a number of dimensional variables in its favor and demonstrated twice the thermal resistance of that on GaN-on-diamond. By using GaN-on-diamond as opposed to GaN-on-SiC, the operating junction temperature was reduced by 40-45% (Figure 3), and the thermal improvement has tripled the areal RF power density from a GaN transistor. However, the relatively low current densities in the GaN-on-diamond devices limited the output power compared to the devices on
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Figure 2. Photograph of a 4-inch GaN-on-diamond wafer [34].
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Figure 3. T he operating temperature of the GaN-on-diamond and GaN-on-SiC HEMT s [38].
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GaN-on-SiC (Figure 4), which may be attributed to the trapping effects rather than the heating effect.
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To avoid the heat barriers caused by the adhesive dielectric layer, the direct bonding without adhesive agent was developed. J. C. Kim et al. used a spark plasma sintering process at $1 0 0 0 ^ { \circ } \mathrm { C }$ with a uniaxial pressure to fabricate the GaN-on-diamond wafers [39]. The highresolution transmission electron microscopy (HRTEM) confirmed the formation of GaN on diamond via the chemical bonding. Unfortunately, the localized hot molten zones of interlayer were observed during the spark plasma environment, bringing out the difficulty using this method.
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The high temperature process in the bonding approaches leads to the considerable stress and the wafer bowing due to the large mismatch of TEC. Besides, the high temperature process may also induce chemistry modification and damages of the bonded structure. To overcome these issues, a low temperature bonding technique was developed. The low temperature wafer bonding is successful in various applications such as the fabrication of silicon-on-insulator (SOI), heterogeneous integration, and advanced packaging at temperature below $4 0 0 ^ { \circ } \mathrm { C }$ [40,41]. One approach at room temperature is to employ the surface activated bonding machine, in which the Ar ion beam at high power was used to active both the surfaces and a Si nano-layer was sputtering deposited as the adhesion layer [42]. After the surface preparations, the two samples were bonded at room temperature by contact and press. But due to the highpower Ar ion deposition, an amorphous diamond layer was formed between diamond and the deposited Si as well as between the deposited Si and GaN, as shown in Figure 5 (a) and (b) by HR-TEM [43]. To experimentally obtain the $T B R _ { e f f }$ between GaN and diamond, the time-domain thermoreflectance (TDTR) was utilized, which is a pump-probe technique that can measure thermal properties of the nanostructures and epitaxial films. The $T B R _ { e f f }$ between GaN and diamond using surfaceactivated bonding (SAB) was estimated to be ∼18m2 K/GW,
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corresponding to a thermal boundary conductance (TBC) of 53 MW/m2 K. When the thickness of Si was reduced to 4 nm (Figure 5 (c) and (d)), the $T B R _ { e f f }$ was further reduced to ∼10 m2 K/GW. However, it is noted that, the yield of the direct bonding using the above methods for the formation of GaN-on-diamond is still low for the larger wafer diameters due to the challenge of uniform polishing of the GaN layer and the bonding process. Mu et al. reported on the 1 cm × 1 cm sized polycrystalline diamond bonded to the GaN/sapphire [42]. Cheng et al. utilized the single-crystalline diamond substrate for the surface activated bonding to GaN and the size was even smaller [43].
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The success of the low-temperature bonding of GaN to diamond enables the device transfer to the diamond technique. The device transfer has the direct advantage of utilizing the standard high yield GaN HEMT process. Chao et al. reported the GaN-on-SiC HEMTs devices transfer to the polycrystalline chemical vapor deposition (CVD) diamond substrate with a maximum drain current density of 1.2 A/mm and peak transconductance of 390 mS/mm [44]. In this approach, a thin layer of Si-based adhesion was utilized and the bonding process was at the temperature of $1 5 0 ^ { \circ } \mathrm { C }$ It was confirmed that the GaN HEMT-on-diamond maintained lower channel temperatures than the original GaN HEMT-on-SiC while delivering 3.6 times higher RF power within the same active area. In 2017, Liu et al. firstly achieved the 3-inch GaN-on-diamond HEMTs device transferred to the diamond substrate at the bonding temperature of $1 8 0 ^ { \circ } \mathrm { C }$ [45]. The 3-inch device wafer was coated with a thermosetting adhesive layer, then bonded face-down onto a 3-inch SiC temporary carrier wafer. A bonding adhesion layer with a thickness of 15-20 nm was deposited onto the exposed GaN as well as on the 3-inch polycrystalline diamond substrate. For a GaN HEMT at the power dissipation of 10 W/mm, the peak junction temperature of the device was decreased from 241 °C to191 °C after transferring to the diamond substrate. A maximum current density of ∼1 A/mm and a power
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Figure 4. Electrical characteristics. (a) I-V characteristics for GaN-on-diamond (solid) and GaN-on-SiC HEMT devices (hollow). (b) output power measured at 10 GHz CW and $V _ { \mathrm { D C } } = 2 0$ Vfor for GaN-on-diamond (solid) and GaN-on-SiC HEMT devices (hollow) [38].
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Figure 5. (a) Cross-sectional HR-TEM images and (b) high-angle annular dark field scanning TEM images of the GaN/diamond interfaces using SAB bonding. (c) and (d) are for the sample with the improved interfaces [43].
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density of 5.5 W/mm CW at 10 GHz with the power added efficiency (PAE) of 50.5% were achieved (Figure 6). By using a finite-element analysis, the $T B R _ { e f f } 0 \mathrm { f } 1 9 \mathrm { m } ^ { 2 } \mathrm { K } / \mathrm { G W }$ was obtained in the GaN-on-SiC device, while the $T B R _ { e f f }$ in the GaN-on-diamond was estimated to be 51 m2 K/GW. Further optimization on the thermal conductivity of the adhesion layer, thickness and bonding process is still needed.
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# 3. Gan epitaxially grown on the diamond substrate
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Another method to achieve the GaN-on-diamond is to grow the GaN and HEMT structures on the diamond substrate. The epitaxial growth is challenging due to the large lattice mismatch and thermal mismatch between GaN and diamond, as shown in Table 1. The lattice mismatch between GaN and diamond is 11.8% [46–49]. The thermal mismatch with different TECs also induces a high tensile strain in the epilayer during the cooling down of the sample after growth. There are a lot of efforts in the GaN deposited on different types of diamond substrates, such as single crystal diamond (SCD) with (110), (111) or (100) orientations, nano-crystalline diamond,
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polycrystalline diamond, or the highly misoriented diamond substrate [49–63]. The growth methods include metal organic chemical vapor deposition (MOCVD), molecular beam epitaxial (MBE), HVPE and resonance plasma enhanced MOCVD (ECR-MOCVD) [49–59].
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The first trial of GaN deposition on the SCD substrate is in 2003. Since the GaN with the device quality can be deposited on sapphire substrates using a buffer layer, in spite of the lattice mismatch of nearly 16.1%, researchers also utilized an AlN nucleation layer to deposit GaN on the type IIa (110) SCD substrate by MOCVD [49]. However, the closely packed GaN grains instead of the smooth surface were observed on the surface. X-ray diffraction (XRD) showed the GaN layer was polycrystalline and hexagonal, with c-plane orientation perpendicular to the substrate. As a result of the carbon incorporation originating from the substrate, a very poor optical quality was determined by photoluminescence.
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In 2003, the epitaxial growth of AlN layer on diamond (100) substrate was improved by plasma-induced MBE [50]. The silicon-doped n-type AlN film on the natural boron-doped p-type diamond substrate formed a hetero-bipolar diode with good rectifying properties and
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(a)
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(b)
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(c）
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(d）
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Figure 6. (a) A 3-inch GaN-on-diamond wafer by substrate transfer process, (b) SEM image of air bridge of a multi-finger device. Pulsed (c) and DC (d) I-V characteristics of GaN HEMT before (dashed lines) and after (solid lines) substrate transfer.
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surprisingly efficient light emission in the spectral range from 2.7 to 4.8 eV under forward bias. The AlN was wurtzite with the [0001] direction on the diamond. However, the quality of the GaN was still unacceptable on the diamond (100) substrate. The XRD pole figure analysis established the presence of the two domains of epitaxial layer, namely (0001)<10-10 > GaN//(001)[110] diamond and (0001)<10-10 > GaN//(001)[1-10] diamond, which were 90° rotated with respect to each other [51]. The presence of these domains was explained by the occurrence of areas of (2 × 1) and (1 × 2) surface reconstruction of the diamond substrate. When applying highly misoriented diamond substrates toward the [110] diamond direction, one of the growth domains was suppressed and the crystalline quality of GaN was improved. However, the surface of the GaN was still rough and could not be utilized for the HEMT devices.
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The quality of the GaN was improved when the SCD (111) substrate was utilized. In 2009, Dussaigne et al. reported the GaN grown on (111) SCD substrate by ammonia-source molecular beam epitaxy (NH -MBE) using an AlN buffer layer [52]. The reflectance high
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energy electron diffraction (RHEED) pattern demonstrated the good quality and smooth surface. The wurtzite-structured GaN grown on (111) diamond was with [0001] crystallographic direction. The root mean square roughness from atomic force microscopy (AFM) was 1.3 nm, while the surface was still with the grain boundary morphology. In addition, the cracks were observed for the 1 µm-thick GaN layer. The full-width at half maximum (FWHM) of the XRD rocking curve around (002)-plane was 1500 arcsec. For the GaN grown on the (111) orientated SCD substrate, the films has an in-plane epitaxial relationship [10-10] GaN//[110] diamond. The pre-treatments of the diamond surface were helpful to eliminate the formation of the amorphous layer or the inversion domains [53]. In 2010, Dussaigne et al. used a strain engineered interlayer to improve the surface morphology of the GaN grown on the (111) SCD substrate by MBE using ammonia as nitrogen source [54]. This strain engineered interlayer composed of a sequence of 200-nm-thick AlN layer and 200 nm-thick GaN layer. The rms of the 800 nm-thick GaN epitaxial layer was reduced to 0.6 nm, and no cracks were observed on the
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surface. The mobility of the 2DEG was improved to be 750 cm2 /Vs with the sheet carrier density of 1.4 × $1 0 ^ { 1 3 } \mathrm { c m } ^ { - 2 }$ from the AlGaN/GaN heterojunction, as shown in Figure 7. For the HEMT devices, the 200 nm gate length devices showed 0.73 A/mm maximum drain current
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Figure 7. T emperature dependent Hall effect measurements: (a) experimental data (opened squares) together with calculated electron mobility considering different limiting factors (blue dashed/dotted lines) and (b) sheet carrier density [54].
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density and $f _ { T }$ and $f _ { m a x }$ cut-off frequency of 21 and 42 GHz [55].
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The progress of GaN grown on the SCD (111) substrates was also achieved by the NTT Basic Research Laboratories. In 2011, Hirama et al. reported the AlGaN/GaN HEMTs with a low thermal resistance grown on SCD (111) substrate by using MOCVD [56]. Benefitting from a high temperature cleaning process at $1 2 0 0 ^ { \circ } \mathrm { C }$ in the hydrogen ambient, the formation of the amorphous interfacial layer was prevented on the diamond substrate, which was a crucial process to obtain the atomically abrupt AlN/diamond heterointerface [57]. After the thermal cleaning, a 180 nm-thick AlN buffer was grown, followed by 20-period AlN/GaN multilayers, then the AlGaN/GaN heterostructure was grown with the GaN thickness of 600 nm. Although the surface morphology did not show atomic steps, the metal-polar was confirmed for the structure using convergent beam electron diffraction in this study. The two-dimensional electron gas (2DEG) was successfully achieved, with the sheet carrier density of $1 . 0 \times 1 0 ^ { 1 3 } \mathrm { c m } ^ { - 2 }$ and mobility of 730 cm2 /Vs. The AlGaN/GaN HEMTs with a 3 µm-gate length showed the maximum drain current of 220 mA/mm, cut-off frequency of 3 GHz and maximum frequency of oscillation of 7 GHz. The thermal resistance between HEMT and diamond is 4.1 K mm/W, as shown in Figure 8. The 0.4 µm-gate-length HEMT showed a dc drain-current density of 770 mA/ mm and breakdown voltage of 165 V [58]. The RF power density of 2.13 W/mm was obtained (Figure 9). This is the first report on the RF power operation of the AlGaN/GaN HEMTs epitaxially grown on the diamond substrate.
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The nano-crystalline and poly-crystalline diamond were also proposed as the template for the epitaxial growth of GaN to achieve the effective thermal
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Figure 8. (a) Setup for measuring the temperature distributions from the side of the AlGaN/GaN HEMT s on the diamond or SiC substrates. Temperature distribution of the AlGaN/GaN HEMT s on (b) diamond and (c) SiC substrates at a dissipated power of 2W (3.2W/mm). (d) Dissipated power dependence of device temperature for AlGaN/GaN HEMT s on the diamond and SiC substrates. Closed and open squares indicate the temperatures for diamond and SiC substrates, respectively [56].
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Figure 9. RF large-signal characteristics of an AlGaN/GaN HEMT at 1 GHz [58].
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dissipation [60–63]. The diamond was firstly deposited on the silicon substrate, therefore, there is no limitation in the substrate size. A low-temperature buffer layer is typically utilized before the deposition of GaN films. Unfortunately, the GaN layer was not pure wurtzite structure and the polycrystalline form was typically observed [60–62]. Recently, an epitaxial lateral overgrowth (ELO) of single-crystalline thick GaN films were reported on the polycrystalline diamond [63]. The polycrystalline diamond was deposited on the GaN/Si wafers using hot filament CVD. The GaN was grown on the window region between the diamond stripes. A lower pressure, higher V/III ratio, higher temperature, and GaN window mask openings along [11̅00] resulted in enhanced lateral growth of GaN. Complete lateral coverage and coalescence of GaN were achieved over a [11̅00]-oriented 5 μm-wide GaN window between 5 μm diamond stripes. The advantage of the ELO growth is no interlayer formation between diamond and GaN, which will be promising for the effective thermal dissipation. However, there is no device demonstration or the $T B R _ { e f f }$ results from this technique.
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The interface thermal property was analyzed for the HEMT device epitaxially grown on the SCD substrate by N-plasma MBE [64]. A transient interferometric method, in combination with a three-dimensional model, was used to describe a pulsed operation of a transistor-like heater, and a micro-Raman technique was used in a steady state. The thermal conductivity of the diamond was found to be 2200 W/mK, and a relatively lower $T B R _ { e f f } \mathrm { o f } < 1 0 \mathrm { m } ^ { 2 } \mathrm { K } / \mathrm { G W }$ was achieved. The temperature increase in the device was saturated after 1 µs from the start of the heat dissipation and the normalized device thermal resistance of about 3.5 K mm/W was achieved.
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# 4. Diamond epitaxially grown on GaN wafers
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The uniqueness of the direct CVD diamond growth on GaN is that the diamond can be deposited as close as possible to the Joule heating location of the HEMTs. This approach is highly effective for the thermal dissipation of HEMTs. However, there are three limitations that restrict this technique. First, the presence of hydrogen during the growth of CVD diamond requires a dielectric layer such as $\mathrm { S i N _ { x } }$ utilized to protect GaN layer, contributing to the large $T B R _ { e f f }$ for the devices [65]. Second, the diamond nucleating layer begins with many small grains, resulting in a poor thermal conductivity [66]. Third, to avoid the degradation of the GaN, low temperature deposition is needed. However, it has been shown that lowering temperature below $6 0 0 ^ { \circ } \mathrm { C }$ using conventional $\mathrm { H } _ { 2 } / \mathrm { C H } _ { 4 }$ based growth results in the growth of the poor-quality diamond [67]. In addition, the stress is another unavoidable problem. In general, diamond will only nucleate on the carbide forming materials like many refractory metals or Si and will not outgrow in the single crystal phase even on cubic substrates (except for growth on Ir [68]). There is no report on the SCD deposited on GaN, as an alternative, the nano-crystalline or polycrystalline diamond were fabricated [36, 69].
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The first attempt to deposit diamond films onto hexagonal GaN was by the group of Oba and Sugino [46, 70], who deposited diamond on (0001)-oriented GaN films using microwave plasma CVD. To prevent the etching to the GaN surface, a carburiziation was conducted. The growth of oriented, heteroepitaxial isolated diamond crystals on the GaN surface was achieved, but the crystals did not coalesce into a continuous film due to the low nucleation density. In 2006, May et al. reported the growth of continuous layers of diamond on GaN using a hot filament CVD technique [67]. They found that there was a competition between the rate of diamond deposition and the rate of GaN decomposition, which determined whether net deposition or etching occurred. When the temperature was higher than $6 0 0 ^ { \circ } \mathrm { C } .$ , the GaN decomposed, evolving gaseous $\mathrm { N } _ { 2 }$ which created pinholes in the growing diamond layer or caused it to delaminate. Lowering the substrate temperature below $6 0 0 ^ { \circ } \mathrm { C }$ resulted in a prohibitively low growth rate and poor-quality diamond.
|
||||
|
||||
The earliest pieces of diamond-on-GaN wafer were obtained by growing the poly-crystalline diamond on a dielectric-coated Ga-face GaN-on-Si wafer, then the Si was etched away, leaving behind an N-face GaN-ondiamond wafer [71]. The thickness of the CVD poly-crystalline diamond was 25 µm. By 2006, the Ga-face GaN-on-diamond HEMT was obtained. In this process, firstly the GaN-on-Si epitaxy was bonded onto a temporary Si carrier, then the host Si substrate was etched away, followed by the deposition of a 50 nm-thick
|
||||
|
||||
dielectric (such as SiN ) onto the exposed rear of the GaN. The polycrystalline diamond was finally deposited onto the dielectric for the GaN-on-diamond HEMT devices by using a hot filament CVD process. The wafer size at that time was over 10 × 10 mm2 area, and the epi-surface exhibited countless particulates that obstructed device processing. The electrical current collapse for the first HEMT on diamond was observed. In 2012, the thickness of the polycrystalline diamond was increased to 100 µm [72], and the device performance was further improved [73]. Over 7 W/mm output power density at 10 GHz was reported, along with the peak PAE over 46% and power gain over 11 dB at 40 V.
|
||||
|
||||
In the above process of diamond deposited on GaN, the residual stress was propagated into the GaN layer and caused local defects and uneven bonding of the wafer after the carrier wafer was removed, leading to the wafer bow and warp. The interaction between the intrinsic stress and the built-in stress in the GaN affected the electrical behavior of the device. The effects of the increased stress represent a significant reliability concern for the device, especially when considering the function and life time of the device [43, 74–78]. Jia et al. utilized a double-sided diamond deposition technique to reduce the stress problems [79]. A tensile stress of ∼0.5 GPa was obtained in the GaN layer of the GaN-ondiamond structure, and the crystal quality of the GaN
|
||||
|
||||
was observed to not change significantly after the wafer transfer process. A seamless interface with a ∼10 nm SiC and a thin Al-Si–N intermediate interfacial layer were observed, which facilitated the adhesion between the GaN and the heat dissipation diamond layer. However, the interfacial layer may lead to a high $T B R _ { e f f }$ Zhou et al. investigated the interface thermal property of GaN and polycrystalline diamond with SiN and AlN barrier layers as well as without any barrier layer [80,81] (Figure 10). The $T B R _ { e f f }$ was estimated by TDTR method with a 100 nm-thick Au as the transducer layer, which had a value of ∼ 6.5 m2 K/GW when an ultrathin SiN barrier layers were utilized. The direct growth of diamond onto GaN results in one to two orders of magnitude higher $T B R _ { e f f }$ due to the formation of a rough interface. AlN barrier layers can produce a $T B R _ { e f f }$ as low as that with SiN barrier layers in some cases. However, the $T B R _ { e f f }$ is rather dependent on growth conditions. A decreasing diamond thermal resistance with increasing growth temperature was also observed. To compensate the thermal stress between GaN and diamond during the epitaxial growth, Cuenca and Smith proposed a membrane-based technology [35, 82]. From their analysis based on the analytical models, the bow for a membrane structure with small sizes were underestimated and the bow could be reduced if the membrane was pre-stressed to become flat at CVD temperatures. The
|
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|
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|
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|
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|
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|
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|
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|
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Figure 10. (a) sample structure and thermoreflectance measurement scheme. (b) Thermoreflectance signal as as function of time of GaN-on-diamond samples with different barrier layer. Lines represent the experimental value and dots represent an analytical model fitted to the experimental values. (c) Unnormalized and (b) normalized sensitivity curves for the GaN-SiN-diamond samples, with the sensitivity of △R/R corresponding to ±10% change in each input parameter in the model. The laser heating pulse stops at 10 ns [80].
|
||||
|
||||
sample was from the GaN-on-Si. The Si substrate was selectively removed, and the windows were formed for the polycrystalline diamond deposition using microwave plasma CVD. The diamond was grown on the
|
||||
|
||||
|
||||
(a)
|
||||
|
||||
|
||||
（(b)
|
||||
Figure 11. (a) The NC D growth was conformal across MESA edges and (b) no cracking or blistering of the growth NC D films even for films as thick as 6.2 µm.
|
||||
|
||||
etched exposed N-polar AlN epitaxial nucleation layers. The high-quality diamond/voi-free AlN interfaces were confirmed from microstructure analysis. This approach is the important demonstration to solve the thermal stress issue during the epitaxial growth of diamond heat spreader on the GaN-based materials and devices.
|
||||
|
||||
The nanocrystalline diamond (NCD) films deposited on the fabricated InAlN/GaN HEMTs devices were reported in 2011 by Alomari et al. [83] (Figure 11). The thermally stable contacts were prepared by depositing a Ta diffusion barrier on the Cu contacts. Then the HEMTs structure were passivated with a thin Si based interlayer (containing the passivated layer and Si-nucleation layer). The NCD nucleation and growth steps were conducted in a hot filament CVD chamber at $7 5 0 \mathrm { - } 7 7 0 ^ { \circ } \mathrm { C } .$ A nucleation density of about $3 \times 1 0 ^ { 1 0 }$ nuclei/cm2 was achieved. The average grain size on the top was around 120 nm in diameter. Raman spectroscopy indicated a dominant diamond peak as the main constituent while the presence of the graphitic phase at the grain boundaries. No degradation or change in the HEMT DC characteristics was observed despite the high temperature of the diamond overgrowth process. Tadjer et al. reported the NCDcapped HEMTs exhibited approximately 20% lower device temperature from 0.5 to 9 W/mm dc power device operation [84]. NCD-capped HEMTs exhibited the improved carrier density and sheet resistance, but the on-state resistance and the breakdown behaviors were degraded, as shown in Figure 12. The selective growth of the NCD was reported by Ahmed et al. [65] on the AlGaN/GaN wafer by hot filament CVD. A thin layer of $\mathrm { S i N _ { x } }$ by plasma enhanced CVD, deposited prior to seeding and diamond deposition, was found to be essential to protect the AlGaN/GaN wafer. A methane concentration of 3.0% was used to increase the diamond growth rate and faster surface coverage. Excellent selectively and minimal surface damage to AlGaN were achieved. The
|
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|
||||
|
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|
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|
||||
Figure 12. (a) Non-confocal Raman thermography profile of the device channel temperature of AlGaN/GaN HEMT s with and without NC D heat spreading. (b)Temperature-depth confocal Raman profile of the HEMT structures under dc bias. (c) Confocal Raman Si TO peak intensity depth profile showing the GaN/Si interface [84].
|
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|
||||
dual side deposition of the NCD was also reported with a AlN as the dielectric layer [85].
|
||||
|
||||
The interface thermal properties between GaN and NCD diamond were improved by Smith et al. using a two-step mixed-seeding method [86]. It was found that the mixture of microdiamond and nanodiamond seeding led to a low $T B R _ { e f f }$ While the diamond directly grown onto GaN was proved to be unsuccessful due to the poor adhesion. The two-step mixed-seeding method gave $T B R _ { e f f }$ values lower than 6 m2 K/GW, 30 times smaller than those of films using nanodiamond seeding alone. Such remarkably low thermal barriers obtained with the mixed-seeding process of microdiamond and nanodiamond offer a promising route for the fabrication of high-power GaN HEMTs using diamond as a heat spreader.
|
||||
|
||||
The double-side diamond integration to the HEMTs devices were also developed to improve the heat dissipation. In 2019, Fujitsu Limited and Fujitsu Laboratories Ltd. deposited diamond films on the front surface of the HEMT device. They also bonded the SCD on the back side of HEMTs using SiC interlayer, as shown in Figure 13 [89]. The nanodiamond films were grown at a temperature of $6 5 0 ^ { \circ } \mathrm { C }$ without degrading the transistors’ performance. With the NCD layer on the front side, the amount of heat generated during HEMT operation was reduced by approximately 40% compared to that without the diamond film, and the temperature can be lowered by $1 0 0 ^ { \circ } \mathrm { C }$ or more. By combining the heat dissipation from the back side of the GaN HEMT with SCD substrate, the operating temperature is expected to be reduced by approximately 77%.
|
||||
|
||||
# 5. Interface thermal property between GaN and diamond
|
||||
|
||||
Thermal boundary resistance is an essential concern for GaN-on-diamond transistors especially when they are operating at high-power densities. According to the diffuse mismatch model (DMM), the theoretical limits of $T B R _ { \mathrm { e f f } }$ between GaN and diamond is 3 m2 K/GW [88]. However, the measured values are far from the ideality. The interface transition layer between GaN and
|
||||
|
||||
diamond plays a key role for the contribution of the $T B R _ { e f f }$ no matter if the GaN is bonded to diamond, epitaxially grown on diamond or the diamond grown on GaN devices. The experimental methods that typically used to determine $T B R _ { e f f }$ include the TDTR technique, transient thermoreflectance (TTR) technique, and the three-dimensional (3D) Raman thermography mapping method. The principles of the TDTR and TTR methods are similar. In the TDTR measurement, a pump laser is utilized to periodically heat the sample surface and a probe laser monitor the thermal reflectivity signal of the transducer metal (Al or Au). The reflected intensity tracks the temperature change of the surface, and the normalized reflected intensity is equal to the normalized surface temperature change. Therefore, the change in the thermal reflectivity of the surface is directly proportional to the temperature change. The signal, which is picked up by a photodetector and a lock-in amplifier, is fitted with an analytical heat-transfer solution to infer the unknown parameters. The 3D Raman thermography mapping exploits the temperature induced phonon shift in a material, with respect to a reference phonon frequency measured at ambient temperature [89–92]. The stress can be simultaneously obtained by the simultaneously analyzing the multiple phonon modes [92]. By using a three-dimensional finite element thermal model, the temperature dependent thermal properties can be extracted [93]. The $T B R _ { e f f }$ can also be extracted by analyzing the HEMTs device performance using the steadystate heat conduction model [94].
|
||||
|
||||
For the GaN or HEMT devices grown on diamond substrate, the buffer layers with the lattice-mismatched induced high-density dislocations, are the main reason for the high $T B R _ { e f f }$ In the bonding process or the diamond deposition on GaN, since the gallium does not readily form a carbide, $\mathrm { S i N _ { x } }$ is typically used to form an interlayer. $\mathrm { S i N _ { x } }$ has a low thermal conductivity of 1-2 W/mK, which introduces an additional thermal resistance. For the polycrystalline diamond deposited on the GaN with a $\mathrm { S i N _ { x } }$ interlayer, the SiN contributes to most of the GaN-on-diamond interface thermal resistance, resulting in a $T B R _ { e f f }$ of more than 30 m2 K/GW, adding >20% to the total device resistance [95]. In
|
||||
|
||||
|
||||
Figure 13. T he heat-spreading method using the double-side diamond and the heat dissipation efficiency [87].
|
||||
|
||||
Table 2. Summary on the $T B R _ { e f f }$ at the interface between GaN and diamond using different integration methods and different measurement methods.
|
||||
|
||||
<table><tr><td>Integration method</td><td>Interlayer</td><td>thickness</td><td>\(TBR_{eff}\)(m2K/GW)</td><td>Measurement</td><td>Ref.</td></tr><tr><td>Direct vdW bonding</td><td>No</td><td>0</td><td>220±70</td><td>TTR</td><td>[98]</td></tr><tr><td>RT surface-activated bonding</td><td>Si</td><td>10 nm</td><td>~18</td><td>TDTR</td><td>[43]</td></tr><tr><td>RT surface-activated bonding</td><td>Si</td><td>4 nm</td><td>~11</td><td></td><td></td></tr><tr><td>Bonding</td><td>Thermosetting adhesion</td><td>15-20 nm</td><td>51</td><td>Device finite-element analysis</td><td>[45]</td></tr><tr><td rowspan="2">HT bonding</td><td>Adhesion</td><td>3-55 nm</td><td>27-31</td><td>TDTR</td><td>[99]</td></tr><tr><td>Adhesion</td><td>3-55 nm</td><td>25-29</td><td>DC joule heating</td><td></td></tr><tr><td>HT bonding</td><td>SiNx</td><td>22 nm</td><td>17</td><td>TDTR</td><td>[100]</td></tr><tr><td>GaN grown on SCD using MBE</td><td>Not indicated</td><td>Not indicated</td><td><10</td><td>TDTR</td><td>[64]</td></tr><tr><td>Hot-filament CVD diamond on GaN</td><td>dielectric</td><td>25 nm</td><td>27</td><td>3D Raman mapping</td><td>[93]</td></tr><tr><td>MPCVD diamond on GaN</td><td>dielectric</td><td>50 nm</td><td>36</td><td></td><td></td></tr><tr><td>CVD polycrystalline diamond grown on GaN</td><td>SiN</td><td>100 nm</td><td>38.5±2.4</td><td>TDTR</td><td>[101]</td></tr><tr><td>CVD polycrystalline diamond grown on GaN</td><td>AIN</td><td>100 nm</td><td>56.4±5.5</td><td></td><td></td></tr><tr><td>CVD diamond on GaN</td><td>dielectric</td><td>50 nm</td><td>18</td><td>Raman</td><td>[102]</td></tr><tr><td>CVD diamond on GaN</td><td>SiNx</td><td>30 nm</td><td>29</td><td>TDTR</td><td>[103]</td></tr><tr><td>CVD diamond on GaN</td><td>SiNx</td><td>28 nm</td><td>12</td><td>TTR</td><td>[95]</td></tr><tr><td>CVD diamond on GaN</td><td>SiNx</td><td>~5 nm</td><td><10</td><td>TDTR</td><td>[105]</td></tr><tr><td>CVD diamond on GaN</td><td>SiNx</td><td>~5 nm</td><td>6.5</td><td>TTR</td><td>[81]</td></tr><tr><td>CVD diamond on GaN</td><td>SiC</td><td>~5 nm</td><td>30±5.5</td><td>TTR</td><td>[104]</td></tr><tr><td>CVD Mixed-size diamond seeding on GaN</td><td>No</td><td>0</td><td><6</td><td>TTR</td><td>[86]</td></tr></table>
|
||||
|
||||
addition, the diamond nucleation layer is usually composed of a few 10 s of nm poor-quality, small-grained diamond [96], which also contributed to the $T B R _ { e f f }$ The direct diamond growth on GaN or bonding to the GaN layer usually shows much weaker interfaces, although there are rare reports on $T B R _ { e f f }$ assessments. It is generally known that weaker interface results in higher $T B R _ { e f f }$ [97,98]. Table 2 summarizes the reported $T B R _ { e f f }$ at the GaN-on-diamond interface using different integration methods and different measurement methods.
|
||||
|
||||
# 6. Summary and outlook
|
||||
|
||||
In this paper, the fabrication of GaN-on-diamond wafers using different methods and the properties of the materials and the fabricated HEMT devices are systematically reviewed. The bonding of GaN or the well-fabricated AlGaN/GaN HEMTs device with diamond can maintain the quality of both the GaN devices and diamond substrate. However, the dielectric interlayers are necessary for either the high-temperature or room-temperature bonding along with an amorphous layer induced by the surface activation. This interlayer impedes the heat flow from the device channel, leading to a large $T B R _ { e f f }$ The growth technique of the GaN or AlGaN/GaN HEMTs structures on the SCD substrates were developed in recent years. A relatively lower $T B R _ { \mathrm { e f f } } ~ { < } 1 0 \mathrm { m } ^ { 2 } \mathrm { K } / \mathrm { G W }$ was reported at the interface between epitaxial GaN and diamond substrate. However, although the HEMTs devices are demonstrated, the crystalline quality of the material and the mobility of the HEMT devices are still far from those grown on the conventional substrates of sapphire, Si, SiC and free-standing GaN substrates due to the large lattice mismatch and thermal mismatch. The CVD
|
||||
|
||||
growth of the polycrystalline or nanocrystalline diamond on the GaN or HEMTs devices has the uniqueness of the direct growth as close as possible to the Joule hot spots, which may be highly effective for the thermal dissipation. However, the damage to the GaN by hydrogen during CVD growth and the less nucleation of the diamond restrict the film quality, leading to a poor thermal conductivity of diamond and large $T B R _ { e f f }$ In addition, the large thermal expansion coefficient between diamond and GaN results in the stress problems in the GaN-on-diamond wafers, leading to the layer cracking and wafer bow and impact the electrical performance of the devices. Up to now, a variety of efforts have been performed to challenge the above problems with different methods. Without doubt, the heat dissipation using diamond as heat spreader for the AlGaN/GaN HEMTs devices is a highly effective way to reduce the operation junction temperature compared to the devices on sapphire, Si and SiC substrates. Although the large $T B R _ { e f f }$ exists between GaN and diamond, Fujitsu laboratory has reduced the device temperature during HEMT operation by more than 40%, and the temperature can be lowered by $1 0 0 ^ { \circ } \mathrm { C }$ or more due to the high thermal conductivity of diamond [87]. Nevertheless, to take the full advantage of the GaN technology for the high-power applications, the reduction of the $T B R _ { e f f }$ between GaN and diamond is still a challenge. Novel strategies and concepts are still required for the effective thermal management of GaN-based power devices using the diamond heat spreader.
|
||||
|
||||
# Disclosure statement
|
||||
|
||||
No potential conflict of interest was reported by the author.
|
||||
|
||||
# Funding
|
||||
|
||||
This work was supported by the JST-PRESTO Grant No. JPMJPR19I7, and World Premier International Research Center (WPI) initiative on Materials Nanoarchitectonics (MANA), Ministry of Education, Culture, Sports, Science & Technology (MEXT) in Japan, and National Key Research and Development Program of China (No.2018YFE0125700).
|
||||
|
||||
# Notes on contributor
|
||||
|
||||
Dr. Liwen Sang is the Independent Scientist at the International Center for Materials Nanoarchitectonics (MANA) in National Institute for Materials Science (NIMS), in Japan. She is also the JST-PRESTO researcher under the support of Precursory Research for Embryonic Science and Technology (PRESTO) program, Japan Science and Technology Agency. After receiving her Ph.D degree in Physics from Peking University, she went to NIMS, Japan as the postdoctoral researcher, and then was promoted to the permanent position in NIMS. Her current research interest is the interface engineering for III-V nitride materials and devices.
|
||||
|
||||
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# Heat-spreading diamond films for GaN-based high-power transistor devices
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M. Seelmann-Eggebert a,, P. Meisena , F. Schaudela , P. Koidla , A. Vescanb , H. Leier b
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a Fraunhofer Institut fur Angewandte Festkorperphysik, Tullastr. 72, D-79108 Freiburg, Germany ¨ ¨ b DaimlerChrysler Hochfrequenzelektronik, D-89081 Ulm, Germany
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# Abstract
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We discuss the potential of heat-spreading films with respect to improving the performance of thermally limited high-power high-frequency GaN-FET devices and report on successful diamond deposition on GaN-FETs. Detailed conditions for process compatibility with GaN-FET technology are discussed and shown to be satisfied by the low-temperature deposition process developed. 2001 Elsevier Science B.V. All rights reserved.
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Keywords: Device modeling; Nucleation; Metal semiconductor field-effect transistor MESFET ; Processing Ž .
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# 1. Introduction
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Owing to the combination of high cut-off frequencies, breakdown voltages, saturation velocities and operating temperatures, GaN-based field effect transistors FETs have a great potential for high-frequency Ž . power amplifiers, offering an increase in power output of at least an order of magnitude in comparison with GaAs FETs of comparable device design 1,2 . A limita- - tion of the performance of GaN is the rise in operating temperature caused by heat dissipation, which leads to large leakage currents 3 and reduced channel mobili- - ties 2 . -
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One approach to reduce the operating temperature is to spread the heat from the highly localized source over a larger part of the transistor area. Heat spreading can be achieved by deposition of an electrically insulat-
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ing but highly thermally conducting film. Distinguished by these film properties, diamond is the material of choice. Owing to its excellent heat conductivity -, which exceeds 20 W $\mathrm { c m } ^ { - 1 } ~ \mathrm { K } ^ { - 1 }$ at room temperature, chemical vapor-deposited CVD diamond is used forŽ . heat-spreading coolers. Although the thermal conductivity of CVD diamond reduces with decreasing thickness 4 , we found it to exceed that of gold, even at a - thickness as low as 2 m.
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However, as for the deposition temperature, plasma exposure and non-invasive seeding of the diamond deposition process need to be fundamentally redesigned to satisfy the compatibility requirements of GaN devices. In this paper, we demonstrate experimentally that CVD diamond can be deposited on GaN-FETs without any degradation of the transistor characteristics by fabrication of the first heat-spread transistor prototypes.
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Before we report on the technical details of diamond deposition on GaN-FETs, we discuss some results of thermal simulations. The thermal efficiency of the dia-
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Fig. 1. Sketch of the device geometry: a model used for the thermal simulations; and b enlarged cross-section of the transistor finger. Ž . Ž .
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mond spreading-layer is analyzed and compared with other approaches to the thermal management of power FETs.
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# 2. Thermal modeling of GaN-FETs
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Obtained by dicing a chip from the wafer, a GaN-FET is located on the surface of a cube-like slab. As sketched in Fig. 1, the FET dimensions are much smaller than those of the chip, which therefore have little influence on the thermal device performance. In the FET structure, the heat source is filament-like. Although the filament length is much greater than the thickness of the epilayer, the filament diameter is much smaller, and the heat is practically spread in the plane of the GaN layer. Also, there is already a significant temperature drop in the GaN layer and the device temperature can be less influenced by the choice of the substrate material than expected beforehand. For cost reasons, FET power devices would be preferably fabricated from GaN-structures grown on sapphire rather than SiC substrates, although the latter have a 10-fold higher heat conductivity.
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For our model simulations, a chip $5 0 0 \times 5 0 0 ~ \mu \mathrm { m } ^ { 2 }$ in area was chosen. The GaN layer $( \kappa = 1 . 3 \mathrm { W } \mathrm { c m } ^ { - 1 } \mathrm { K } ^ { - 1 } )$ is assumed to have a thickness of 1 m and to be grown on a sapphire substrate of 300 m thickness $\overline { { ( } } \ l _ { \mathsf { K } } = 0 . 4 6 \ \mathrm { ~ W ~ } \mathrm { c m } ^ { - 1 } \ \mathrm { ~ K } ^ { - 1 } )$ . In the center of the chip surface was a mesa $( 1 0 0 \times 1 2 5 \times 0 . 5 ~ { \mu \mathrm { m } } ^ { 3 } )$ with a single-finger FET of gate width 100 m and gate length 0.25 m. The gatesource and gatedrain distances were 1 m each. All contact pads were $9 0 \times 1 2 0 ~ \mu \mathrm { m } ^ { 2 }$ . Extending from the edge of the gate contact over a distance of 0.15 m towards the drain, the heat source was assumed to be 25 nm below the surface and to have a height of 15 nm. Heat generation was assumed to be uniform over the heat-source volume 5 . -
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The modeling results are discussed in terms of thermal impedance 5,6 rather then temperature. The local - thermal impedance is the temperature rise as mea- Ž
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|
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sured with reference to the heat sink normalized to . the heat power dissipated per gate-width unit as an Ž arbitrarily chosen characteristic device length . To esti- . mate the interdigital crosstalk of multifinger devices, it is convenient to analyze the thermal impedance profile Ž . TIP of a single FET-finger as a plot along the distance from the center of the finger in the plane of maximum temperature 6 i.e. a line just below the - Ž GaN surface in the cross-section of Fig. 1b . Since the . TIPs of different fingers are very similar, the temperature profiles over a comb of fingers can be obtained from a single TIP by lateral translation and subsequent superposition. The introduction of the TIP is useful owing to two simple scaling rules for stationary heat flow: for a considered thermal-impedance profile the temperature is proportional a to the heat load and b Ž . Ž . to the reciprocal gate width, if the whole geometry is rescaled with no change in shape. The peak temperature in the device is obtained by multiplying the peak impedance with the heat dissipated per gate-width unit.
|
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|
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The curves shown in Fig. 2 are thermal simulation
|
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|
||||
|
||||
Fig. 2. Thermal impedance profiles of GaN-FETs for different thermal setups: a bare finger; b 3- Ž . Ž . Ž . m gold bridge as thermal shunt; c 3-m diamond spreading layer; d gold bridge in flip-chip geometry; Ž . and e spreading layer in flip-chip geometry. InŽ . $\mathrm { ( a ) \mathrm { - } ( c ) , }$ the heat sink is at the substrate bottom, in d and e at the top. Ž . Ž .
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results for the single-finger device sketched in Fig. 1a operating under different thermal conditions. Despite the asymmetric position of the heat source with respect to the gate contact, differences in the left and right branch of the curves in Fig. 2 are negligibly small.
|
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The uppermost curve represents the situation of the GaN-FET finger without any thermal precaution. The peak thermal impedance, $\dot { R _ { \mathrm { o } } } = 2 9 . 5 \ \dot { \mathrm { K } } \ \mathrm { m m } \ \mathrm { W } ^ { - 1 }$ , obtained by the simulation is only approximately half the value predicted by the Smith formula for the considered heat source geometry embedded in a sapphire matrix 5 . Hence, the GaN epilayer, with a compara- - tively high thermal conductivity itself, results in a significant reduction in the operating temperature. In Fig. 2a, the heat-spreading effect of this layer is seen as a broad appearance of the TIP and a slow decrease at large distances x from the gate $( \Delta T \sim 1 / \sqrt { x } )$ . This behavior implies a comparatively strong thermal coupling between multiple FET fingers if placed at a typical distance of 30 m: the respective coupling impedance $R _ { \mathrm { c } }$ is approximately one third of $R _ { \mathrm { o } } .$ .
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Conventional thermal shunts are formed by thick goldair bridges $( \kappa = 3 \mathrm { ~ W ~ c m } ^ { - 1 } \mathrm { ~ K } ^ { - 1 } )$ attached to the gate contact and a large fraction of the chip area. In our model calculation, the gold bridge was 3 m thick and as sketched in Fig. 1b connected to the large Ž . drain and source contact pads via a 0.2-m thick insulating SiN layer $( \ l _ { \mathsf { K } } = 0 . 0 1 \hat { 6 } \mathrm { ~ W ~ c m } ^ { - 1 } \mathrm { ~ K } ^ { - 1 } )$ . The thermal design reduces the thermal peak impedance to 70% of its initial value, however, the coupling impedance is lowered only by 10% Fig. 2b . Hence, the situation Ž . regarding thermal crosstalk is not improved.
|
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A drastic temperature reduction is found if a closed spreading layer of diamond is deposited by use of Ž $\overset { \cdot \mathrm { ~ ~ \hat { ~ } { ~ \theta ~ } ~ } } { \left. \mathrm { ~ \bf { { K } } ~ } \right. } = 3 \mathrm { ~ \bf { W } ~ } \mathrm { { { c m } ^ { - 1 } ~ } } \mathrm { { \bf { K } } ^ { - 1 } }$ , fine-grained CVD diamond of poor thermal quality is assumed . Protecting the exposed . surface areas of the transistor, a 20-nm thick SiN layer was included in the calculation. The thermal impedance peak is reduced to 40% of the original value, but the $R _ { \mathrm { c } } / R _ { \mathrm { o } }$ ratio increases further. The large improvement in $R _ { \mathrm { o } }$ with respect to the thermal-shunt approach is a consequence of the lateral distance of the heat source and gate contact. Covering the heat source completely, the film bridges this gap.
|
||||
|
||||
Appreciable thermal crosstalk is common to the three considered situations Fig. 2a,b,c and results from the Ž . position of the heat sink at the bottom of the substrate, i.e. in the thermal far field. Flip-chip designs bear an appreciable advantage over backside-cooled spreading or shunt designs, if the sink can be placed in the near field and, consequently, crosstalk is substantially reduced. Although technically impossible to realize, it is instructive to place the heat sink directly on top of the bridge or spreading layer. The gold bridge design with topside cooling brings the $R _ { \mathrm { c } } / R _ { \mathrm { o } }$ ratio down to 0.02, although the peak temperature reduction is approxi-
|
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|
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mately the same as for the diamond spreading-layer with backside cooling. If a respective flip-chip set-up could be realized with the use of a closed spreadinglayer, the temperature rise during operation could be reduced by a factor of 5.2 with a crosstalk ratio $R _ { \mathrm { c } } / R _ { \mathrm { o } }$ of 0.01.
|
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|
||||
In practice, the apparent advantages of the flip-chip approach are less pronounced. Since relatively thick thermal bumps are required to mediate the bonding of the heat sink to the chip surface, the device temperature is lowered by heat spreading in the thermal bumps rather than by near-field heat flow to the sink. Nevertheless, to achieve high cooling efficiencies, both thermal management approaches require coupling of the film to a large area over the heat source a condition much easier to satisfy with a dielectric than with a metal.
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# 3. Process requirements
|
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|
||||
In view of its superior thermal and dielectric properties, CVD diamond appears to be the material of choice for heat-spreading applications. However, hostile conditions for deposition impede this application of CVD diamond on delicate semiconductor devices. High quality diamond is obtained in a methanehydrogen plasma at elevated deposition temperatures $( 8 0 0 ^ { \circ } \mathrm { C } ) .$ . Deposition at lower temperatures is possible, but brings about losses of quality and low growth rates 7 . For - GaN devices, which are themselves grown at temperatures near $1 0 0 0 ^ { \circ } \mathrm { C } ,$ a temperature of $\mathrm { \bar { 5 } 0 0 ^ { \circ } C }$ appeared to be an appropriate upper limit for diamond deposition, mainly implied by stability considerations of the FET contacts. On silicon substrates, we realized and routinely grow diamond films at this temperature, with thermal conductivities exceeding that of gold 3 W Ž $\mathsf { c m } ^ { - 1 } \ \mathsf { K } ^ { - 1 } )$ , a thickness $> 3$ m and growth rates of $0 . 2 ~ \mu \mathrm { m } ~ \mathrm { h } ^ { - 1 }$ . However, on epitaxial GaN films, diamond deposition is impossible, due to rapid GaN etching $( > 1 \mu \mathrm { m } \mathrm { h } ^ { - 1 } )$ in the plasma, with the eventual formation of gallium droplets. A further problem may occur for p-doped material, by rapid diffusion of atomic hydrogen from the plasma into the GaN matrix.
|
||||
|
||||
# 4. The protective layer
|
||||
|
||||
In view of the obvious instability of GaN in the CVD plasma, the question arises as to how diamond films can be deposited on GaN-based FET devices. However, this apparent obstacle can be overcome by the use of a suitable protective layer satisfying the following requirements. The protective layer should be plasmaresistant and impervious to hydrogen. With regard to the high-temperature cycle employed, it should show
|
||||
|
||||
|
||||
Fig. 3. IR transmission spectra of: a plane 300- Ž . m sapphire substrate; b 500 nm SiN on sapphire after 30-min CVD plasma expo- Ž . sure; and c same layer after 2-h vacuum annealing at 550 Ž . C.
|
||||
|
||||
good adhesion properties to GaN and diamond. Seeding properties of the protective layer are important for stability and seed formation. High heat conductivity is desirable, although not necessary, if plasma protection is warranted, even at a very small thickness of the interlayer.
|
||||
|
||||
AlN, $\mathrm { S i O } _ { 2 }$ and SiN layers were investigated and found to satisfy these requirements, but SiN was finally chosen, mainly in view of process compatibility for the entire device fabrication. Crystalline $\mathrm { S i } _ { 3 } \mathrm { N } _ { 4 }$ has a heat conductivity of 0.3 W $\mathrm { c m } ^ { - 1 } \ \mathrm { K } ^ { - 1 }$ ; however, for thin microcrystalline films, much lower values are reported - 8 . Measurements on CVD-SiN layers routinely used in the standard fabrication process yielded a conductivity of 0.016 W $\mathrm { c m } ^ { - 1 }$ $\mathbf { K } ^ { - 1 }$ 9 . Even upon long-term - exposure 10 h , films of this CVD-SiN material were Ž . not etched by the deposition plasma.
|
||||
|
||||
However, SiN films of 0.10.2 m thickness showed a trend of wrinkle formation after prolonged exposure, indicating local delamination 10 . IR transmission - studies implied some migration of atomic hydrogen through the SiN films. After plasma exposure, absorption features corresponding to SiH and NH stretching vibrations are observed, indicating that hydrogen is trapped in the SiN layer Fig. 3 . The hydrogen features Ž . are appreciably diminished upon annealing in vacuum. Hydrogen diffusion is likely to be much less efficient in the active parts of the device, since these become quickly passivated by the growing diamond overlayer.
|
||||
|
||||
# 5. Seeding
|
||||
|
||||
Appropriate seeding is required to achieve a high nucleation density and to rapidly form a closed diamond film. Common seeding procedures, such as mechanically polishing with diamond powder, are not
|
||||
|
||||
suited for structured micro-devices. We therefore attempted to seed by means of an ultrasonic treatment in a dispersion of diamond powder in water or methanol. This approach yielded generally high nucleation densi-Ž ties in the order of $1 0 ^ { \overline { { 1 0 } } }$ 2 cm with good uniformity, . even over edges of the device structure, and facilitated quick overgrowth of the GaN device. However, the protective SiN coating was found to be damaged by this treatment, even when the treatment was short and diamond powder with a sub-m particle size was used. After a few minutes of plasma exposure, the surface appearance of ultrasonically seeded samples became spotty and the SiN film was observed to peel off locally at these spots.
|
||||
|
||||
Ultrasonic seeding was also found to deteriorate the transistor performance. At the typical pinch-off voltage of 6 V, large leakage currents of approximately 10% of the saturation current were found after the ultrasonic treatment. The observed change in the electrical characteristics indicated damage of the gate electrode caused by the impact of fast diamond particles.
|
||||
|
||||
Owing to the failure of the conventional approaches, an alternative non-invasive seeding method was developed, based on the sedimentation of fine diamond particles from an agitated emulsion. An advantage of this technique is its independence from the surface properties of the substrate. With this seeding technique, very homogeneous and uniform diamond films have been grown on 2-inch wafers of silicon and glass.
|
||||
|
||||
To achieve a selective area growth for diamond films, the sample surface was structured by selective seeding. To avoid diamond growth on specific areas, such as the contact pads, these were covered by photoresist. After the seeding procedure, the photoresist was dissolved in hot acetone or dimethylformamide. The seed layer was completely removed with the photoresist. Hence, diamond grew only on the exposed areas of the samples, whereas unseeded regions remained practically free of deposits.
|
||||
|
||||
# 6. The deposition process
|
||||
|
||||
Diamond deposition was performed in a plasma-CVD ellipsoid reactor 11 operating at 2.45 GHz with a - microwave power up to 6 kW and a power density of 100 W cm3 . The sample was located at the bottom of the reactor on a water-cooled stage. The deposition temperature was adjusted by variation of the process pressure or heat-resistance of the stage. For low-temperature deposition, a pressure in the range 70110 mbar was chosen. At higher pressures, the heat flux density exceeded a critical value, causing thermal cracking 12 of the thin 2-inch sapphire substrates due - to temperature inhomogeneities.
|
||||
|
||||
Low-Temperature nucleation of the film proved to be a critical step. To form a closed film within a period of no longer than 10 min, a temperature of at least 500C as measured by a pyrometer operating at a Ž wavelength of 1000 nm and a largely increased con- . centration of methane 4% was required. After suc- Ž . cessful nucleation as monitored by interferometry , Ž . the methane content of the process gas was set to 1% and, optionally, the temperature was reduced. The following parameters are a typical example of the process conditions: at a pressure of 80 mbar, the heat flux density at the sample surface was 30 W cm2 . If the deposition temperature of 500C is adjusted by a suitable choice of the thermal resistance of the stage, a growth rate of $0 . 2 5 ~ \mu \mathrm { m } ~ \mathrm { h } ^ { - 1 }$ is obtained.
|
||||
|
||||
Adhesion of the diamond films was problematic if a large-area deposition was attempted. If the thickness exceeded approximately 1 m, spontaneous flaw formation was observed and the diamond film delaminated as a result of compressive thermal stress built up during cooldown. Somewhat surprisingly, the diamond films turned out to adhere very well on selectively seeded FET samples. On the structured chips, adhesion was aided by separation grooves which were left unseeded and defined individual spreading layers for each FET.
|
||||
|
||||
With the process developed, diamond spreading layers were routinely deposited on GaN-FETs. As demonstrated by the REM image of Fig. 4, the diamond layer is distinguished by very good selectivity and exhibits remarkably abrupt edges at the contacts.
|
||||
|
||||
The devices investigated in this study were fabricated using a standard GaN-transistor process with gates defined by optical lithography. More details on the fabrication process are found elsewhere 13 . -
|
||||
|
||||
For checks on the compatibility of the CVD-diamond deposition with the overall FET fabrication process, a piece of a wafer was electrically DC characterized before diamond deposition and the protective layer was then put down. Next, areas to be excluded
|
||||
|
||||
|
||||
Fig. 4. REM image of a two-finger GaN-FET with a 0.7-m diamond film deposition temperature 440 Ž . C .
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 5. a Output; and b transfer characteristics of a two-finger Ž . Ž . GaN-FET before and after deposition of a 0.7-m thick diamond film.
|
||||
|
||||
from deposition such as the contact pads were cov- Ž . ered with photoresist. After selective seeding, the diamond film was grown. The protective layer was then removed from the contacts by dry etching in a $\mathrm { C F } _ { 4 } / \mathrm { O } _ { 2 }$ plasma and the FET characteristics were recorded for a second time. Fig. 5 shows a comparison of the output and transfer characteristics before and after diamond deposition at a deposition temperature close to $4 0 0 ^ { \circ } \mathrm { C } .$ Fig. 5 demonstrates a well-working transistor, which was subject to only minor alterations in the process of diamond deposition. However, above $4 4 0 ^ { \circ } \bar { \mathrm { C } } ,$ serious degradation of the NiAu gate contact occurred, leading to failure of the transistors. EDX measurements revealed that this deterioration had to be attributed to alloying, which caused the gate contact to lose its Schottky character. With an improved GaN-FET processing scheme, stable device operation was accomplished, even at temperatures above $5 1 0 ^ { \circ } \mathrm { C } .$ In the absence of gate-metal alloying phenomena, no signs of transistor degradation after diamond deposition were found. However, for stable gate contacts, an increase in Schottky barrier height was observed after the plasma treatment, an effect typical for heat-treated GaN transistors, caused by an interfacial reaction between the gate metal and the semiconductor.
|
||||
|
||||
In a recent run, transistors with the new stable Schottky contacts were investigated at a deposition
|
||||
|
||||
temperature of $4 8 0 \mathrm { { } ^ { \circ } C }$ . Even after deposition of $2 { \cdot } { \mu } \mathrm { m }$ diamond, the FETs remained fully operational.
|
||||
|
||||
# 7. Summary and outlook
|
||||
|
||||
Heat-spreading diamond films are shown to be an useful approach to reducing the operating temperature of GaN-FETs and, hence, to have the potential for boosting power output of high-frequency GaN devices. Direct CVD deposition of diamond on GaN-FETs is demonstrated to be feasible and completely compatible with state-of-the-art GaN device-processing technology. To achieve this compatibility, a novel gentle seeding process and a low-temperature $( < 5 0 0 ^ { \circ } \mathrm { C } )$ deposition process was developed, involving a protective layer. Temperature-resistant gate contacts are required to allow the deposition temperature to exceed $5 0 0 ^ { \circ } \mathrm { C } .$ . To our knowledge, this is the first demonstration of successful CVD diamond deposition directly on an operational IIIV semiconductor circuit. Detailed experiments proving the cooling efficiency of the spreading diamond still remain to be performed.
|
||||
|
||||
# Acknowledgements
|
||||
|
||||
H. Guttler and M. Hirsch of DaimlerChrysler and E. ¨
|
||||
|
||||
Worner, C. Wild and R. Sah of Fraunhofer IAF are ¨ gratefully acknowledged for helpful discussions. This work was supported by the BMBF.
|
||||
|
||||
# References
|
||||
|
||||
- 1 Y.-F. Wu, B.P. Keller, S. Keller et al., IEICE Trans. Electron. E82-C 11 1999 1895.Ž . Ž .
|
||||
- 2 C.E. Weitzel, Institue of Physics Conference Series, 142, 1996 Ž . 765 chapter 4 . Ž .
|
||||
- 3 E. Kohn, W. Ebert, A. Vescan, Isr. J. Chem. 38 1998 105. Ž .
|
||||
- 4 E. Worner, in: B. Dischler, C. Wild Eds. , Low-Pressure Syn- ¨ Ž . thetic Diamond, Springer-Verlag, Berlin, 1998, p. 137 chapter Ž 9 ..
|
||||
- 5 R. Anholt, Electrical and Thermal Characterization of MES-FETs, HEMTs and HBTs, Artech, Norwood, 1994, pp. 5863.
|
||||
- 6 R. Anholt, Solid State Electron. 42 1998 849.Ž .
|
||||
- 7 Y. Muranaka, H. Yamashita, H. Miyadera, Diamond Films Technol. 5 1995 1. Ž .
|
||||
- 8 S.R. Mirmira, L.S. Fletcher, J. Thermophys. Heat Transfer 12 Ž . Ž . 2 1998 121.
|
||||
- 9 H. Guttler, personal communication. ¨
|
||||
- 10 G. Gille, B. Rau, Thin Solid Films 120 1984 109. Ž .
|
||||
- 11 M. Funer, C. Wild, P. Koidl, Surf. Coat. Technol. 116 ¨ 119 Ž . 1999 853.
|
||||
- 12 K.J. Gray, H. Windischmann, Diamond Relat. Mater. 8 1999 Ž . 903.
|
||||
- 13 A. Vescan, R. Dietrich, A. Wieszt et al., Institute of Physics Conference Series, 166, 1999 503 chapter 7 . Ž . Ž .
|
||||
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|
||||
# State-of-the-art synthesis and post-deposition processing of large area CVD diamond substrates for thermal management
|
||||
|
||||
W.D. Brown a,b,\*, R.A. Beera a,b, H.A. Naseem a,b, A.P. Malshe a,b,c
|
||||
|
||||
$^{a}$ High Density Electronics Center (HiDEC), University of Arkansas, Fayetteville, AR 72701, USA $^{b}$ Department of Electrical Engineering, University of Arkansas, Fayetteville, AR 72701, USA $^{c}$ Materials and Manufacturing Research Laboratory (MRL), Department of Mechanical Engineering, University of Arkansas, Fayetteville, AR 72701, USA
|
||||
|
||||
# Abstract
|
||||
|
||||
Primarily due to its outstanding thermal conductivity and high electrical resistivity, diamond is an ideal heat spreader for a variety of applications such as multichip modules (MCMs), laser diode arrays, power modules, etc. For these and similar applications, there is a requirement for the synthesis and post-deposition processing of high quality, stress-free, large area $(1 - 100\mathrm{cm}^2)$ , CVD diamond substrates. Although the thermal characteristics of CVD diamond are primarily determined by proper nucleation and growth conditions, post-deposition processing such as polishing, planarization, drilling/cutting, and metallization are required for the practical application of diamond as a heat spreader. Such processes should be fast, compatible with conventional electronic packaging, adaptable to large area fabrication, environmentally-safe, and economically-viable. In the past few years, significant technological advances have been made in all these areas. Furthermore, the cost of these processes has been decreasing steadily so that fabrication of diamond-based electronic products is becoming affordable. This paper reviews the present technological and economic status of CVD diamond for thermal management applications.
|
||||
|
||||
Keywords: Synthesis; Post-deposition processing; Cvd diamond substrates; Thermal management
|
||||
|
||||
# 1. Introduction
|
||||
|
||||
Rapid changes in the electronics industry are driven by the attractiveness of smaller, faster, and lighter weight electronic systems. Consequently, multichip packaging technology is receiving widespread attention. The use of multichip modules (MCMs) promises to increase packaging density and system performance beyond what is otherwise possible with advances in VLSI and surface mount technology. As is the case for most advanced technologies, the drive towards high performance multichip modules has given rise to a number of engineering challenges. In advanced electronic packages, where high speed, high power chips are mounted shoulder-to-shoulder on large circuit boards, heat spreading and removal become major issues. Typically, thermal management substrate materials for electronic packages have been limited to silicon, alumina, and to a much lesser extent, AlN, SiC, and glass/ceramics. However, as the power dissipation of ICs continues to increase,
|
||||
|
||||
heat dissipation and removal will be major issues in future MCMs. More than likely, diamond will play a significant role in the solution to these performance challenges.
|
||||
|
||||
# 1.1. Why diamond for heat spreaders?
|
||||
|
||||
For the single chip or multichip module, or any high density electronics packaging to be successful and reliable, efficient thermal management (TM) is essential. Diamond has an excellent thermal conductivity ( $k = 2000\mathrm{W / m}\cdot \mathrm{K}$ ) for natural diamond and about 700-1600 W/m·K for CVD diamond, a low thermal expansion coefficient ( $\approx 10^{-6}$ ), high electrical resistivity ( $>10^{12}\Omega \cdot \mathrm{cm}$ ), and high mechanical strength (Young's modulus $\approx 10^{11}\mathrm{Nm}^{-2}$ ). These properties of diamond surpass those of all the established substrate materials such as copper, silicon, alumina, aluminum nitride, etc., and make it an ideal heat spreader. Recent advances in CVD diamond deposition technology make it possible to fabricate large area ( $10\times 10\mathrm{cm}$ ) diamond substrates in the laboratory at a reasonable cost. The availability
|
||||
|
||||
of such freestanding diamond makes possible the practical implementation of such a novel heat spreader.
|
||||
|
||||
# 1.2. Thermal considerations
|
||||
|
||||
In the investigation described here, a popular software package, ANSYS, (version 5.0SASI, Houston, PA), which employs the finite element method for thermal simulation, was used to observe the effects of substrate thickness parameters on TM [1]. It was assumed that the contact resistance between materials (for example, an IC and the substrate) is zero. Also, heat loss due to radiation is neglected. For all simulations, the substrate was assumed to be a square with each side being $10.16\mathrm{cm}$ in length. The power dissipated on the top surface of the substrate was $10\mathrm{Wcm}^{-2}$ for a total power of $1032.256\mathrm{W}$ dissipated uniformly on an area of $103.2256\mathrm{cm}^2$ . This is an extreme situation for most electronic packaging applications. The two opposite edges were kept at a constant temperature of $300\mathrm{K}$ with adiabatic boundary conditions applied to the other two edges and the bottom surface of the substrate. Thus, the maximum temperature rise is expected to be in the center with isotherms parallel to the two opposite edges held at $300\mathrm{K}$ . For calculation purposes, the thermal conductivity $(k)$ of the diamond substrate was assumed to be isotropic thus avoiding any thermal resistance caused by grain boundaries in the diamond.
|
||||
|
||||
Fig. 1 is a plot of the maximum temperature as a function of diamond thickness for the simulation conditions noted above. The thermal conductivity was assumed to be $1500\mathrm{W / m}\cdot \mathrm{K}$ . As the thickness of the diamond increases, its contribution to the reduction of temperature becomes smaller. This trend has an important implication in determining an optimum value for the thickness of the substrate. Currently, a substrate thickness considered sufficient for MCM application is typically $1000~{\mu\mathrm{m}}$ . According to the simulation results, diamond substrates $20 - 30\%$ thinner can be used with
|
||||
|
||||
similar TM performance. For example, the rise in temperature for a diamond substrate of $800\mu \mathrm{m}$ thickness under the conditions noted above is $107.54\mathrm{K}$ . This result suggests that the cost of growing CVD diamond can be reduced by limiting the thickness of a substrate to the maximum value required for a specific application.
|
||||
|
||||
# 1.3. CVD diamond substrate fabrication-related problems
|
||||
|
||||
# 1.3.1. Diamond synthesis
|
||||
|
||||
In state-of-the-art synthesis, CVD diamond films are deposited at high temperatures $(>750^{\circ}\mathrm{C})$ either by localized or bulk heating in a mixture of a carbon precursor gas (methane, acetylene, etc.) and a graphite etchant gas (hydrogen) in the presence of an activation agent(s) such as IR radiation, microwave radiation, a d.c. arc, r.f. radiation, or a laser(s) [2]. Presently available CVD diamond equipment, such as d.c. arc jet, microwave plasma, and r.f. plasma systems, are capable of growing diamond films as large as $10\times 10\mathrm{cm}$ . However, films synthesized using various types of activation agents typically have chemical and morphological non-uniformities over the surface and throughout the volume of the material [3]. Also, large diamond substrates can exhibit high intrinsic stresses that result in warping unless deposition conditions are tightly controlled. In general, the higher the thermal conductivity, the higher the stress. This limits the range of thermal conductivities available for large area, thermal management substrates [3].
|
||||
|
||||
These techniques are used to deposit diamond over larger and larger areas in order to reduce the cost (per square) of the material. This approach does decrease the cost to some degree, but it also introduces the need for a laser cutting capability in a manufacturing process which presents an added expense. Another factor that must be addressed is the fact that electronic packages are available in various shapes, sizes, and materials
|
||||
|
||||
|
||||
Fig. 1. Plot of maximum temperature vs. diamond substrate thickness for $k = 1500 \, \mathrm{W/m} \cdot \mathrm{K}$ .
|
||||
|
||||
which requires a capability for depositing diamond onto different materials of both flat and complex geometries.
|
||||
|
||||
# 1.3.2. Diamond post-synthesis processing
|
||||
|
||||
Diamond growth in the initial stages of deposition progresses by nucleation at mechanically-induced and/or randomly-seeded and/or thermally-favored sites because of statistical thermal fluctuations at the substrate surface. Depending on the growth surface temperature, pressure, and reactive environment conditions, favored crystal orientations dominate the competitive growth process. Consequently, the resulting films have a random polycrystalline structure and a rough surface morphology. Large surface roughnesses $(R_{\mathrm{a}} = 2 - 15\mu \mathrm{m})$ often limit the TM efficiency of diamond substrates because of large and numerous surface pits which result from the presence of microcavities in the as-grown bulk material [4]. As a result, post-deposition processing is required if CVD diamond is to be used in many electronic packaging applications. Several novel approaches to post-deposition polishing of CVD diamond films have been investigated recently, including laser/ion beam/plasma treatment, hot metal treatment, and chemical-assisted mechanical polishing and planarization (CAMPP) [5].
|
||||
|
||||
Unfortunately, these polishing techniques do not eliminate "microcavities" in diamond substrates because diamond crystals grow faster in a direction normal to the substrate surface than parallel to it resulting in columnar growth. During growth, these crystals grow into each other creating microcavities throughout the material (Fig. 2). The presence of microcavities prevents any polishing process from yielding a pit-free surface. This, in turn, presents serious problems for photolithographic processes, such as the formation of metal traces, and die bonding in applications requiring uniform thermal contact between the die and substrate. These surface
|
||||
|
||||
|
||||
Fig. 2. SEM micrographs of microcavities in CVD diamond.
|
||||
|
||||
pits also present a problem for attachment of large die by introducing stresses. Furthermore, the sharp edges of the microcavities lead to an increase in surface nonuniformities after electroplating of a metal layer [6]. The size and density of these microcavities can possibly be reduced, but not eliminated, by increasing the density of nucleation sites on the substrate and depositing at a lower rate. At the present time, the only practical way of eliminating these surface pits is by "filling-for-planarization" [7].
|
||||
|
||||
Because of the attractiveness of CVD-diamond for passive electronics applications, reliable metallization systems must be available. Furthermore, in order to produce thick interconnects, plating is the preferred method of applying a metal, such as copper or gold, to the diamond. Unfortunately, owing to its chemical inertness, diamond is expected to have poor adhesion to metals, especially to gold (Au) - a noble metal best suited for conductor traces because of its excellent electrical conductivity. The use of gold, then, requires a metal adhesion/seed layer. Fortunately, diamond is known to form adhering carbide layers with refractory metals such as Ti, W, Mo, etc., and transition metals such as Cr, Ni, Fe, etc. Cr has been used extensively in MCM technologies as an adhesion promoter and diffusion barrier metal and, since it lies close to the refractory metals in the periodic table, it is expected to have excellent carbide forming properties with diamond. Plated gold or copper can then be used to form the interconnections.
|
||||
|
||||
# 2. Experimental
|
||||
|
||||
Some of the major steps in the fabrication of diamond heat spreaders are: (1) seeding of substrates for the nucleation of diamond growth, (2) surface finishing of diamond substrates, (3) cutting and drilling of diamond substrates, and (4) metallization of diamond substrates. Subsequent sections address these subjects in some detail.
|
||||
|
||||
Raman spectroscopy (RS) was used for the chemical analysis of diamond, scanning electron microscopy (SEM) and/or atomic force microscopy (AFM) were used to study the surface morphology of diamond substrates, and contact surface profilometry and AFM were used for surface roughness analysis of processed diamond heat spreaders. X-ray diffraction was used to determine residual stress in diamond films.
|
||||
|
||||
The thermal conductivity of diamond is an extremely important parameter for thermal management substrates. Various techniques, such as the heated bar technique, the Sinku-Riko modified angstrom technique, the Omega technique, the laser flash technique, the transient grating technique, and the photothermal technique, have been and continue to be investigated for
|
||||
|
||||
thermal conductivity analysis of heat spreaders. A detailed discussion of these techniques is beyond the scope of this paper, but can be found in a recent publication by Grabner et al. [8].
|
||||
|
||||
# 3. Results and discussion
|
||||
|
||||
# 3.1. Seeding for large area diamond growth
|
||||
|
||||
In state-of-the-art CVD diamond deposition, the deposition process is usually initiated by depositing on an iron mandrill or by providing defect sites on a substrate surface. In order to decrease the time necessary to initiate the growth, seeding is often used. This can be accomplished by mechanically abrading the surface using diamond particles to physically generate defect sites. Numerous groups have used this inexpensive approach to accelerate the initiation of diamond growth. Also, small diamond particles, mixed with photoresist, can be uniformly distributed on a substrate surface by spin coating [9]. Once the photoresist is burned off in a plasma, the diamond particles act as nucleation sites for diamond growth. Both of these techniques can be used for small or large area applications. Typically, $10^{7}$ to $10^{9}$ particles $\mathrm{cm}^{-2}$ density can be achieved using these techniques. However, a low nucleation density and/or clumping of diamond particles generally results in material with a significant number of large microcavities in the diamond film. Thus, a need exists for a technique which will yield a very high and uniform nucleation density over the entire surface of the substrate onto which diamond is to be deposited. Such a technique should only be limited by the minimum diamond particle size that can be uniformly deposited onto the substrate surface.
|
||||
|
||||
# 3.2. Large area diamond synthesis
|
||||
|
||||
Two of the most important requirements for any process for depositing large area diamond films are: (1) a high growth rate (at least $5\mu \mathrm{m / h}$ ) and (2) the capability of depositing uniform films over a large area (at least $6.5\mathrm{cm}^2$ ). In the published literature, there are a few techniques being used for the production of thermal management diamond substrates. Some of these techniques are d.c. arc jet CVD, microwave plasma CVD, and hot-filament CVD. Of the other techniques being studied, the most promising approach may be a laser-activated deposition technique. The reported growth rate is about $1\mu \mathrm{m}\mathrm{s}^{-1}$ over a $1\mathrm{cm}^2$ area [10].
|
||||
|
||||
In our laboratory, we have deposited diamond onto silicon using the microwave plasma CVD technique. The deposition system is made by Wavemat, Inc. and operates at the TM 012 mode at $2.45\mathrm{GHz}$ . In this system, uniform and continuous diamond films have
|
||||
|
||||
been deposited over $75\mathrm{mm}$ silicon wafers using the photoresist seeding technique with $4\mathrm{nm}$ diamond particles. Nucleation densities of $>10^{8}\mathrm{cm}^{-2}$ are routinely obtained.
|
||||
|
||||
# 3.3. Intelligent quality control using optical emission spectroscopy (OES)
|
||||
|
||||
An optical emission spectrum of a microwave plasma showing the different reactive species present during diamond deposition is shown in Fig. 3. The atomic traces from hydrogen and the molecular structure from CH, $\mathbf{C}_2$ , and $\mathrm{H}_{2}$ are clearly visible. However, these transitions only provide direct information for the excited states. To infer information related to the chemically-important ground state densities, a knowledge of the electron energy distribution function (EEDF) is needed. Using argon as an actinometer, we can study the population of ground state atomic hydrogen. Because OES is relatively easy to implement, the determination of in situ correlations between OES and diamond growth parameters is of great interest. Numerical simulations which account for the non-Maxwellian EEDF will facilitate this determination.
|
||||
|
||||
Our present actinometry data show that increasing methane concentrations depress the EEDF and negligibly affect the atomic hydrogen ground state. The effect on the EEDF presumably results from increased electron-molecular vibrational coupling. Our data also indicate that increasing power increases the atomic hydrogen ground state density but only marginally increases the energy of the EEDF. Numerical simulations have been combined with experimental optical emission measurements of free and bound-excited electron number densities to demonstrate the potential of OES as a quantitative diagnostic tool for microwave CVD reactors [11].
|
||||
|
||||
# 3.4. Cutting and drilling of diamond substrates
|
||||
|
||||
Cutting of CVD diamond substrates is an essential step in the fabrication of thermal management substrates. Free-standing diamond substrates are usually manufactured by deposition over a large circular mandrill and often have a lip (or collar) around the outer edge caused by deposition on the edge of the mandrill. This creates a need for a method of cutting substrates into either circular wafers without the collar or substrates of various other sizes and shapes. However, the cutting of single-crystal gem diamond and polycrystalline CVD diamond is different in several respects. The hardness and chemical inertness of CVD diamond, along with its polycrystalline structure, present a serious challenge to conventional substrate cutting techniques. The problem is even more complicated if one desires to cut thick diamond films deposited on a substrate with
|
||||
|
||||
|
||||
Fig. 3. OES spectrum of a typical $1.6\mathrm{kW}$ microwave plasma with $\mathrm{H}_{2}$ and $\mathrm{CH}_4$ gases.
|
||||
|
||||
different thermal properties. In fact, although diamond cutting technology is new to the CVD diamond industry, it was developed a few decades ago for cutting single-crystal diamond slabs (not gems). Typically, CVD diamond is cut using a pulsed Nd-YAG laser. The wavelength, power, and repetition rate of the laser, and the chemical quality of diamond, critically determine the definition of the cut, i.e., the cutting-induced burr, the contamination, melting, and refusing of the material, and micro-cracking of the material. Also, the definition of a corner can depend on the proper choice of laser wavelength. Furthermore, the cutting speed of a laser can be enhanced by providing proper photo-chemistry or certain gases at the workpiece.
|
||||
|
||||
The formation of vias for substrate-to-substrate interconnects is another important technology in a series of processing steps necessary for the fabrication of diamond substrates, particularly 3-D multichip modules (MCMs). Vias, which are typically $100 - 150\mu \mathrm{m}$ in diameter, are filled with metal to define metal interconnects through the diamond plane. Depending on the size and design of an electronic system, the number of vias can vary from a few hundred to a few thousand on a single substrate and diamond, due to its hard and chemically-inert nature, presents a formidable challenge to their formation.
|
||||
|
||||
Laser drilling is the only practical approach to the formation of vias in CVD diamond. The challenges are to form very precise diameter vias in a short time with a desirable edge angle, little, if any, wall contamination, and excellent definition of the top surface-hole wall junction. A further complication in state-of-the-art CVD diamond substrates is the existence of internal stresses. Drilling of a substrates changes its stress pattern, and
|
||||
|
||||
thus, the flatness of the substrate. Although, a significant amount of research has been conducted in this area, very little has been published because the techniques used and results are considered proprietary. A most promising approach to this problem consists of drilling the film while it is submerged in a liquid using a focused Q-switched Nd-YAG laser. To date, drilling has been performed in air, de-ionized water, and a few other solutions (Fig. 4) [12-16]. Research on this approach to via drilling of diamond is continuing.
|
||||
|
||||
# 3.5. Lapping and polishing
|
||||
|
||||
The chemical inertness, hardness, polycrystalline nature, and non-uniform surface chemistry of CVD
|
||||
|
||||
|
||||
Fig. 4. SEM micrograph of a laser drilled hole in CVD diamond performed under water.
|
||||
|
||||
diamond present serious challenges to the development of surface finishing processes (i.e., polishing and planarization). Techniques which have been tried include conventional mechanical lapping, hot metal polishing, chemical-assisted mechanical polishing, plasma etching, ion beam etching, and laser beam trimming. In general, these approaches can be divided into coarse lapping and fine polishing. For example, mechanical lapping and laser trimming can be used to produce a coarse finish (Fig. 5). Using these approaches, the surface roughness of diamond can be reduced from an $R_{\mathrm{a}}$ of $15\mu \mathrm{m}$ to about $1 - 1.5\mu \mathrm{m}$ as determined by contact surface profilometry. If an electronic packaging application requires a further reduction in the surface roughness, a technique such as chemical-assisted mechanical polishing can then be used for fine polishing. This technique is capable of reducing the average surface roughness from an $R_{\mathrm{a}}$ of $1.5\mu \mathrm{m}$ to about $100 - 150\mathrm{nm}$ as measured by contact surface profilometry [16]. Table 1 provides a comparison of the capabilities of these lapping and polishing techniques.
|
||||
|
||||
As noted previously, a close examination of even finely polished diamond surfaces ( $R_{\mathrm{a}} = 50 \mathrm{~nm}$ by contact surface profilometer) using AFM reveals the presence of surface pits resulting from "microcavities" being intersected by the surface plane. Microcavities have been observed in all CVD diamond material independent of the deposition technique. Often, these surface pits are not detected by contact surface profilometry, but they exist and must be addressed by some post-deposition processing technique.
|
||||
|
||||
# 3.6. Planarization-by-filling
|
||||
|
||||
Basically, the "planarization-by-filling" process consists of filling diamond substrate surface pits (microcavi
|
||||
|
||||
|
||||
Fig. 5. SEM micrograph showing as-deposited and laser trimmed (polished) CVD diamond.
|
||||
|
||||
ties) with a polymer, glass, diamond-filled glass, or similar material [7]. The filler is applied as a thin overlayer on the diamond substrate which planarizes the surface. The overlayer can then be polished back to expose the previously polished diamond surface. However, thermal simulation studies of such planarized diamond surfaces have shown that backpolishing is not necessary from a thermal performance point of view. In fact, this planarization technique offers a simple, conventional approach to the reduction of surface roughness without polishing the diamond surface at all, thereby significantly reducing the time and cost of preparing CVD diamond films for electronic packaging applications.
|
||||
|
||||
Fig. 6 shows an AFM plot of a diamond substrate which was coated with polyimide prior to evaporating and defining an aluminum pattern on the surface. The polyimide is about $5\mu \mathrm{m}$ thick with an average surface roughness of $25\mathrm{nm}$ . Testing of the polyimide overcoat yielded an adhesion strength value of about $2500\mathrm{psi}$ . Although the adhesion strength degraded with thermal shock testing, it was still sufficient for use of the planarized diamond substrate in thermal management applications. Fig. 7 shows a planarized and metallized diamond substrate.
|
||||
|
||||
# 3.7. Metallization
|
||||
|
||||
# 3.7.1. Metalization of large area diamond substrates
|
||||
|
||||
Diamond MCMs require complex metallization systems for defining the ground and power planes, and the signal interconnects. In order to realize these required electrical functions, large area metallization, selective metallization, and metal via filling capabilities must be available. In particular, gold (Au) or copper (Cu), due to their low resistivity, are considered to be the ideal metals for MCM interconnects. Depending on the MCM performance requirements, the required metal thickness can range from a few microns to a few tens of microns, and the required interconnect width can be a few tens of microns. For such requirements, plating is preferred over thermal evaporation or sputtering because it is a simple and economical technique. Large area plating processes have been developed for both gold and copper at the University of Arkansas.
|
||||
|
||||
The adhesion of metallization to diamond in MCMs is a reliability concern. Consequently, the adhesion of Au or Cu to diamond must be enhanced by the use of other metals as seed layers prior to plating. It is important to note that the surface pits discussed previously can cause serious blistering of the plated metal if the plating is not performed properly (Fig. 8). However, "planarization-by-filling" can be used to eliminate the blistering problem.
|
||||
|
||||
Table 1 Cost analysis for post-synthesis finishing of CVD-diamond substrates: estimated costs for various processing technologies
|
||||
|
||||
<table><tr><td rowspan="2"></td><td colspan="4">Cost-related parameters (for 3" × 3")</td></tr><tr><td>LT(8 h day-1operation)</td><td>CAMPP(8 h day-1operation)</td><td>Cleaning(8 h day-1operation)</td><td>FP(8 h day-1operation)</td></tr><tr><td rowspan="2">1. Capital cost plus % for installation(% capital cost increase for4" × 4" sample)</td><td>$75 000:</td><td>$47 000:</td><td>$5000:</td><td>$4800:</td></tr><tr><td>laser + table + optics (0%)</td><td>machine + accessories (27%)</td><td>glassware (50%)</td><td>spinner + IR oven + soft bake oven (10%)</td></tr><tr><td>2. Type of consumable</td><td>$120 year-1</td><td>$4800 year-1</td><td>$6000 year-1</td><td>$5000 year-1</td></tr><tr><td>3. Maintenance</td><td>$600 year-1</td><td>$180 year-1</td><td>$60 year-1</td><td>$600 year-1</td></tr><tr><td>4. Energy usage</td><td>100 W</td><td>2.5 kW</td><td>80 W</td><td>60 kW (ovens)</td></tr><tr><td>5. Time for processing/sample</td><td>40 min</td><td>3 h</td><td>30 min</td><td>3.30 h</td></tr><tr><td>6. Rigidity of equipment(i.e., vacuum, and critically)</td><td>Atmospheric process,critical optical alignment</td><td>Atmospheric process,critical sample mounting</td><td>None</td><td>None</td></tr><tr><td>7. Down time to repeat this same process</td><td>5 min</td><td>30 min</td><td>5 min</td><td>2 min (final process)</td></tr></table>
|
||||
|
||||
LT, Laser trimming; CAMPP, chemical-assisted mechanical polishing and planarization; and FP, filling for planarization. Diamond substrate material specifications: (1) substrate size: $3 \times 3 \mathrm{in}^2$ ; (2) initial $R_{\mathrm{a}} = 3 - 5 \mu \mathrm{m}$ (measured by mechanical surface profilometry); (3) final $R_{\mathrm{a}} = 0.25 \mu \mathrm{m}$ (measured by mechanical surface profilometry); (4) starting thickness, $90 \mu \mathrm{m}$ ; (5) final thickness, $700 \mu \mathrm{m}$ ; (6) bow in the substrate, $\leq 25 \mu \mathrm{m}$ ; (7) chemical quality (in terms of thermal conductivity), $12 \mathrm{W/cm} \cdot \mathrm{K}$ ; (8) primary film orientation, (110); (9) substrate without collar; and (10) grain size cariation, $20 - 25\%$ .
|
||||
|
||||
# 3.7.2. Adhesion/seed layers and metal plating
|
||||
|
||||
Owing to its chemical inertness, diamond is expected to have poor adhesion to most metals, especially to gold - a noble metal best suited for conductor traces because of its excellent electrical conductivity. Thus, there is a need for a metal adhesion/seed layer as noted previously. Fortunately, diamond is known to form strongly adhering carbide layers upon annealing at high temperatures $(700 - 900^{\circ}\mathrm{C})$ with refractory metals such as Ti, W, Mo, etc., and transition metals such as Cr, Ni, Fe, etc. [17].
|
||||
|
||||
Some of the metal systems examined for potential use as the adhesion/seed layer for diamond-based MCM metallization systems are Au/Ti, Au/Ti-W, Au/Cr, Au/Ni-Cr and Cu/Cr. These metal systems are generally deposited by evaporation or sputtering and then annealed at temperatures ranging from 150 to $500^{\circ}\mathrm{C}$ . Depending on deposition parameters, such as deposition rate, substrate temperature, pressure, etc., adhesion values ranging from about 3 kpsi to greater than 10 kpsi have been achieved [18]. These adhesion values are more than adequate for MCM metallization although they can be increased by sputter etching of the diamond surface prior to deposition of the metals.
|
||||
|
||||
# 3.7.3. Electroplated gold
|
||||
|
||||
Although gold and copper plating are mature technologies that have been used in the electronics industry for decades, bare, polished, MCM grade CVD diamond, with its rough surface due to the presence of surface pits, presents a plating challenge. If plating of diamond is attempted using the parameters specified by plating solution manufacturers, the roughness of the diamond surface is enhanced. For example, in initial attempts at gold plating of diamond at the University of Arkansas,
|
||||
|
||||
the surface roughness increased from $330\mathrm{nm}$ to $2\mu \mathrm{m}$ for a $4\mu \mathrm{m}$ thick gold layer. This surface roughness is unacceptable for MCM substrates. A thorough investigation revealed that the increase in surface roughness had nothing to do with the gold thickness but, in fact, was related to the plating current density. The current density recommended by the plating solution manufacturer was identified as the problem. Upon reducing the plating current density by a factor of 10, the surface roughness actually decreased with increasing gold thickness. Doubling of this lower plating current density maintains the original surface roughness while yielding an acceptable deposition rate of $2\mu \mathrm{m}\mathrm{h}^{-1}$ . A $4\mu \mathrm{m}$ thick layer has a resistivity of about $4.0\mu \Omega \cdot \mathrm{cm}$ which compares favorably with the standard value for gold of $2.2\mu \Omega \cdot \mathrm{cm}$ .
|
||||
|
||||
Large area plating of diamond substrates (10 cm diameter) for MCM applications can be accomplished by evaporating a $\mathrm{Au} / \mathrm{Cr}$ adhesion/seed layer followed by annealing at a temperature of $300^{\circ}\mathrm{C}$ (Fig. 9). The samples are then gold plated to a thickness of several microns and annealed at $300^{\circ}\mathrm{C}$ . This process yields adhesion values greater than 3 kpsi even after the samples are thermally cycled between 150 and $-65^{\circ}\mathrm{C}$ .
|
||||
|
||||
# 3.7.4. Diamond substrate rework
|
||||
|
||||
Because of the relatively high cost of diamond substrates, research has also been performed to establish a viable method for reclaiming them after they have been metallized. Two wet processes and a lapping technique were investigated. A wet process consisting of cerric ammonium nitrate, perchloric acid, and water was found to be the most effective method for reclaiming diamond. EDS showed no indication of chromium on the sample
|
||||
|
||||
<table><tr><td colspan="2">Image Statistics</td></tr><tr><td>Z range</td><td>2.209 μM</td></tr><tr><td>Mean</td><td>684.54 nm</td></tr><tr><td>RMS (Rq)</td><td>293.22 nm</td></tr><tr><td>Mean roughness (Ra)</td><td>141.42 nm</td></tr><tr><td>Max height (Rmax)</td><td>2.077 μM</td></tr><tr><td>Surface area</td><td></td></tr><tr><td>Surface area diff</td><td></td></tr></table>
|
||||
|
||||
<table><tr><td colspan="2">Box Statistics</td></tr><tr><td>2 range</td><td>277.36 nm</td></tr><tr><td>Mean</td><td>934.20 nm</td></tr><tr><td>Rms (Rq)</td><td>69.134 nm</td></tr><tr><td>Mean roughness (Ra)</td><td>27.572 nm</td></tr><tr><td>Max height (Rmax)</td><td>166.04 nm</td></tr><tr><td>Box x dimension</td><td>20.706 μm</td></tr><tr><td>Box y dimension</td><td>13.176 μm</td></tr></table>
|
||||
|
||||
|
||||
Fig. 6. AFM micrograph of a polyimide planarized CVD diamond substrate.
|
||||
|
||||
after an etch time of $15\mathrm{min}$ in the solution. However, care must be taken to ensure that all the etchant is removed from the sample before it is re-used.
|
||||
|
||||
# 3.7.5. Metallization of vias
|
||||
|
||||
Metal filling of substrate vias is obviously important in MCM technologies because of the multi-level nature of the metal interconnection system. Proper via filling is also critically important to multi-substrate communication in a 3-D MCM architecture. For diamond, which has a graphitization temperature between 700 and $800^{\circ}\mathrm{C}$ , low temperature via filling materials such as metal-filled epoxy or plating can be used. Recently, another approach to via filling using tungsten-copper
|
||||
|
||||
|
||||
Fig. 7. Optical photograph of photolithographically-defined aluminum patterns on a polyimide planarized 2.0 inch diamond substrate.
|
||||
|
||||
|
||||
Fig. 8. SEM micrograph of a metallized diamond substrate on which a blister has been deliberately cut open to reveal multiple microcavities.
|
||||
|
||||
composite has been developed using a technique developed by Micro Substrates Corporation [19]. Although there are several other approaches to via filling, the method chosen to fill vias in diamond must be based on other construction aspects of the substrate, subsequent processing steps in the fabrication schedule, and the desired function of the vias.
|
||||
|
||||
# 4. Economics of thermal management diamond substrates
|
||||
|
||||
At the present time, the electronics industry is extremely cautious about using diamond in packaging because of its cost. As with most products, the introduction of diamond thermal spreaders into electronic products will come down to a trade-off between price and
|
||||
|
||||
|
||||
Fig. 9. Optical photograph of a gold plated 4.0 inch diameter diamond wafer.
|
||||
|
||||
product performance. This probably means that the initial approach to incorporating diamond into electronics will be applications where the use of diamond is critical for proper system operation and the cost is not a prime consideration. Although diamond heat spreader prices have dropped dramatically in the past few years, a further substantial decrease in price is needed before the widespread use of diamond will occur. For users of diamond, the price depends on the specific application. Questions which must be answered are; (1) can the diamond be used as grown or must it be polished; (2) must the sample be polished on one side or both sides; (3) what is the required surface finish; (4) what is the required thermal conductivity; (5) what is the substrate quantity required; and (6) what are the desired substrate dimensions, including thickness? These questions are very similar to those which must be answered when ordering substrates made from any other material. A $10\mathrm{cm}$ diameter diamond substrate $1\mathrm{mm}$ thick contains approximately 140 carats of diamond. As-grown diamond can cost anywhere from $100 to$ 3500 per carat, depending on its quality. Post-synthesis processing such as lapping or polishing add to this cost, and they are very expensive processes. The high cost of post-deposition processing is partially a result of the fact that most vendors are using conventional processing techniques. For example, it takes a long time to lap and polish polycrystalline CVD diamond substrates using techniques developed for polishing gem stones. Non-conventional approaches, such as a combination of laser trimming/quick lapping/filling for planarization are capable of reducing post-deposition processing costs by orders of magnitude as suggested by the data in Table 1.
|
||||
|
||||
# 5. Summary and conclusions
|
||||
|
||||
Although technologies for the deposition of thin film synthetic diamond have existed for over a decade, only
|
||||
|
||||
in the past 5 years have research efforts been concentrated on economical deposition and post-deposition processing of large area diamond thin films for application in electronic packaging. Because of its unique properties, diamond is the ideal thermal management material if its cost is competitive with other materials and if technologies are available to process it. During the past 5 years, significant advancements in diamond synthesis have resulted in the deposition of large area substrates and a substantial reduction in cost. The availability of large area material prompted a concentrated effort to develop technologies, such as lapping, polishing, planarization, cutting, drilling, and metallization, which would permit diamond to be used in electronic packaging applications. Although not mature, these post-deposition processing technologies have evolved to the point that as-deposited diamond can realistically be utilized in thermal management applications. However, a further reduction in cost of both diamond synthesis and post-deposition processing will be necessary before diamond finds widespread use in commercial electronic packaging.
|
||||
|
||||
# References
|
||||
|
||||
[1] A.P. Malshe, S. Jamil, M.H. Gordon, H.A. Naseem, W.D. Brown and L.W. Schaper, Advanced Packaging, September/October 1995, pp. 50-53.
|
||||
[2] J.E. Butler et al., Phil. Trans. R. Soc. Lond., A 342 (1993) 209-224.
|
||||
[3] A.P. Malshe, unpublished work at University of Arkansas, Fayetteville. AR, 1995.
|
||||
[4] A.P. Malshe, G.J. Glezen, H.A. Naseem and W.D. Brown, Proceedings of the Fourth International Symposium on Diamond Materials, The Electrochemical Society, Pennington, NJ, 95-4 (1995) 515-522.
|
||||
[5] D.G. Bhat, D.G. Johnson, A.P. Malshe, H.A. Naseem, W.D. Brown, L.W. Schaper and C.-H. Shen, Diamond Relat. Mater., 4 (1995) 921-929.
|
||||
|
||||
[6] G.J. Glezen, Masters thesis, University of Arkansas, Fayetteville, AR, 1995.
|
||||
[7] A.P. Malshe, W.D. Brown, H.A. Naseem and L.W. Schaper, US patent No. 5,472,370, 1995.
|
||||
[8] J. Grabner, in K. Azar (ed.), in Handbook of Experimental Methods in Electronic Cooling, CRC Press, in press, 1996.
|
||||
[9] R.A. Beera, M.S. Haque, W.D. Brown, A.P. Malshe and H.A. Naseem, Proceedings of Topical Conference on Synthesis and Processing of Materials, AIChE 1994 Annual Meeting, San Francisco, CA, 1994, pp. 65-70.
|
||||
[10] Pravin Mistry, QQC, Inc., Workshop on Characterizing Diamond Films IV, NIST, Gaithersberg, MD, March 4-5, 1996.
|
||||
[11] U.M. Kelkar and M.H. Gordon, Electrochem. Soc. Proc., 96-5 (1996) 75-82.
|
||||
[12] S. Jamil, M.H. Gordon, G.J. Salamo, H.A. Naseem, W.D. Brown and A.P. Malshe, Proceedings of Applications of Diamond Films and Related Materials: Third International Conference, NIST special publication 885, 1995, pp. 283-286.
|
||||
[13] T. Chein, C. Cutshaw, C. Tanger and Y. Tzeng, Proceedings of
|
||||
|
||||
Applications of Diamond Films and Related Materials: Third International Conference, NIST special publication 885, 1995, pp. 257-260.
|
||||
[14] P. Tosin, W. Luthy and H.P. Weber, Proceedings of Applications of Diamond Films and Related Materials: Third International Conference, NIST special publication 885, 1995, pp. 271-274.
|
||||
[15] V.G. Ralchenko, S.M. Pimenov, T.V. Kononenko, K.G. Korotoushenko, A.A. Smolin, E.D. Obraztsova and V.I. Konov, Proceedings of Applications of Diamond Films and Related Materials: Third International Conference, NIST special publication 885, 1995. pp. 225-232.
|
||||
[16] A.P. Malshe, unpublished work at University of Arkansas, Fayetteville, AR, 1995.
|
||||
[17] K.L. Moazed, J.R. Zeidler and M.J. Taylor, J. Appl. Phys., 689(5) (1990) 2246-2254.
|
||||
[18] W.D. Brown, H.A. Naseem, A.P. Malshe, J.H. Glezen and W.D. Hinshaw, Mater. Res. Soc. Symp. Proc., 391 (1995) 59-70.
|
||||
[19] W.E. Wesolowski, R.J. DeKcnipp and M.P. Ram Panicker, Proc. ICEMCM-95, Denver, CO, 1995, p. 146.
|
||||
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|
||||
# Fabrication of free-standing diamond membranes
|
||||
|
||||
M.C. Salvadori a, M. Cattani a, V. Mammana a, O.R. Montciro b, J.W. Ager III b, I.G. Brown b
|
||||
|
||||
$^{\text{a}}$ Institute of Physics, University of São Paulo C.P. 66318, São Paulo, SP, CEP 05389-970, Brazil
|
||||
|
||||
<sup>b</sup> Lawrence Berkeley National Laboratory, University of California Berkeley, CA 94720, USA
|
||||
|
||||
# Abstract
|
||||
|
||||
We describe here a method for fabricating free-standing diamond membranes. Diamond films were deposited on a silicon substrate by microwave plasma-assisted chemical vapor deposition and then part of the substrate chemically removed. The films described here were 15 mm in diameter with thickness of approximately $12\mu \mathrm{m}$ . A novel feature of our approach lies in the method used to obtain the selective dissolution of the substrate; a container with O-rings was used, instead of masks, allowing a fast and clean isotropic dissolution of part of the silicon substrate. The deposited diamond films as well as the free-standing membranes were characterized by scanning and transmission electron microscopy, electron diffraction and Raman spectroscopy.
|
||||
|
||||
Keywords: Diamond; Chemical vapour deposition; Plasma processing and deposition
|
||||
|
||||
# 1. Introduction
|
||||
|
||||
Diamond thin films possess a number of unique chemical and physical properties that make them attractive for a broad range of applications in research and industry. The rapidly developing technology for the growth of polycrystalline diamond films by plasma-assisted chemical vapor deposition (CVD) on a range of substrates has increased interest in this material. Applications of diamond thin films include: wear-resistant coatings for cutting tools, by virtue of its hardness; as thermal management of electronic devices, because its room-temperature thermal conductivity is the highest of all materials; as free-standing windows with good transparency in the visible and infrared region; and as free-standing permeable membranes [1] for use as filters, by virtue of the chemically inert and mechanically resistant nature of diamond. Several CVD methods have been developed and successfully used to produce diamond films such as, for example, hot filament CVD [2], electron-assisted CVD [3], microwave plasma-assisted CVD [4], d.c. discharge CVD [5], and use of the oxygen-acetylene torch [6].
|
||||
|
||||
In this paper we describe a method for fabricating freestanding diamond membranes from a film deposited on silicon. Selective chemical etching of the substrate promotes dissolution of the silicon leaving the diamond membrane intact. The method is particularly attractive because of its simplicity, ease for producing large area membranes, and its low cost.
|
||||
|
||||
# 2. Experimental details
|
||||
|
||||
The diamond films were synthesized by microwave plasma-assisted CVD using a system that has been fully described elsewhere [7]. The growth parameters used here were: 300 sccm for the hydrogen flow rate, 1.5 sccm for the
|
||||
|
||||
|
||||
Fig. 1. Container with O-rings for dissolution of part of the silicon substrate. The sample was loaded on the lower O-ring with the diamond side down, then the upper part of the container was screwed tight so as to sandwich the sample between the two O-rings.
|
||||
|
||||
|
||||
Fig. 2. The circular region inside the square $(18 \times 18 \mathrm{~mm}^2)$ silicon substrate is a free-standing diamond membrane.
|
||||
|
||||
|
||||
Fig. 3. SEM of the top side of the diamond membrane showing morphology typical of CVD-grown polycrystalline diamond film.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 4. (a) Bright-field transmission electron microscopy image of a diamond grain with normal parallel to [110] direction. Twin bands are indicated in the picture, and their signatures indicated in the diffraction pattern. (b) Electron diffraction pattern of the grain shown in (a). (c) High-resolution transmission electron micrograph of a CVD diamond membrane.
|
||||
|
||||
methane flow rate (0.5 vol.% methane), $9.3 \times 10^{3} \mathrm{~Pa}$ for the chamber pressure, $850^{\circ} \mathrm{C}$ for the sample temperature, and a nominal $870 \mathrm{~W}$ for the microwave power. Film thickness was controlled by variation of the growth time between 10 and $48 \mathrm{~h}$ .
|
||||
|
||||
A novel feature of our approach lies in the method used to obtain the selective dissolution of the substrate: a container made of PVC, with Buna-N O-rings, as shown in Fig. 1, was used instead of masks, allowing a fast and clean isotropic dissolution of part of the silicon substrate. The sample (diamond film on its silicon substrate) was loaded on the lower O-ring with the diamond film down. Then the upper part of the container was screwed tight so as to sandwich the sample between the two O-rings. A room-temperature mixture of hydrofluoric acid, nitric acid and acetic acid [8] was used to dissolve the silicon. The HF:HNO₃ volume ratio was 2:1, and the acetic acid was added to prevent violent reaction that can fracture the diamond membrane during the substrate etching. The time required to dissolve the substrate was between 10 and 30 min for a silicon substrate of thickness of about 200 μm.
|
||||
|
||||
Scanning and transmission electron microscopy were used to characterize the deposited diamond films as well as the free-standing membranes. A Jeol JSM-840A scanning electron microscope (SEM) with an accelerating voltage of 25 kV was used to evaluate the surface morphology of the films, as well as the etch profile of the silicon substrate. Transmission electron microscopy (TEM) was conducted in a TOPCON 002B. At 200 kV the point resolution of this microscope is 0.19 nm, which is suitable for viewing [111] lattice fringes of diamond. Samples for TEM were prepared by mounting pieces of thin free-standing membranes (5 μm thick or less) on copper grids and ion milling the films with an Ar⁺ beam at 3.5 kV until perforation occurred. Raman spectroscopy was also carried out to provide additional information on the quality of the membranes produced.
|
||||
|
||||
# 3. Results and discussion
|
||||
|
||||
We have in this way made a number of thin diamond membranes with the central $15\mathrm{mm}$ diameter substrate free. Note that the diameter of the free-standing region is determined simply by the O-ring size, which can readily be increased so as to prepare free-standing films of arbitrary size.
|
||||
|
||||
An example of one of our diamond membranes is shown in Fig. 2, where the diamond film lies within the circular region and the square silicon substrate is $18 \times 18 \mathrm{~mm}^2$ . Fig. 3 shows a SEM of the top side (growth side) of the diamond film, showing morphology that is typical of polycrystalline diamond films.
|
||||
|
||||
The surface morphology of the deposited films consisted mainly of (111) and (100) facets. Transmission electron microscopy also indicated the presence of stacking faults, and micro- and macro-twins, which have been often observed in CVD diamond films. Fig. 4(a) shows a transmission electron
|
||||
|
||||
micrograph of one of the membranes produced with one of the grains oriented with the electron beam parallel to the [011] direction. Observation of stacking faults and twin domains is most easily done under this conditions. In this orientation the stacking faults and twin domain boundaries, which coincide with {111} planes, are seen edge-on, and their signature on the diffraction pattern is easily identifiable. Fig. 4(b) shows the electron diffraction pattern of the grain shown in Fig. 4(a). Diffraction spots resulting from multiple twinning, and streaks resulting from stacking faults or microtwins are observed. The high resolution image of another crystal of the diamond m r rane under similar orientation is also shown in Fig. 4(c). Multiple twinning and stacking faults are easily identified.
|
||||
|
||||
The Raman spectra of the two sides of one membrane are presented in Fig. 5. These spectra are consistent with that of diamond with very low amorphous carbon phase contamination. It is interesting to note that there is slightly more amorphous carbon at the silicon side than on the growth side.
|
||||
|
||||
Fig. 6 shows the back side of the sample, where the diamond film was in contact with the silicon substrate before its chemical dissolution; one can see in this micrograph that the diamond grain size is about $4\mu \mathrm{m}$ . Fig. 7 shows the back side of the diamond film where it adjoins the thicker silicon substrate; the smooth region on the right hand side of the figure
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 5. Raman spectra of both sides of a free-standing diamond membrane.
|
||||
|
||||
|
||||
Fig. 6. SEM of the back side of the diamond membrane, where the diamond film was in contact with the silicon substrate before its chemical removal. The diamond grain structure is clearly shown.
|
||||
|
||||
|
||||
Fig. 7. SEM of the back side of the membrane near the edge. The smooth part (right) is the free-standing diamond film and the rough part (left) is the silicon substrate.
|
||||
|
||||
is the free-standing diamond film and the rougher part on the left side is the silicon substrate. Note that the silicon profile near the free-standing diamond film is sharp, in spite of the fact that the chemical dissolution was isotropic. The film
|
||||
|
||||
thickness of about $12\mu \mathrm{m}$ was determined by breaking a film grown under similar condition and measuring it under SEM.
|
||||
|
||||
# 4. Conclusion
|
||||
|
||||
We have fabricated a number of diamond membranes by selective dissolution of the silicon substrate using a container with O-rings, instead of masks, allowing a fast and clean isotropic removal of a chosen part of the substrate. The test diamond membranes, made in the work described here, were circular with a diameter $15\mathrm{mm}$ . The size of the free-standing region can readily be increased.
|
||||
|
||||
# Acknowledgements
|
||||
|
||||
This work was supported by the Fundação de Amparo à Pesquisa do Estado de São Paulo and the Instituto de Física da Universidade de São Paulo, Brazil. We would also like to acknowledge the support and use of the facilities of the National Center for Electron Microscopy at the Lawrence Berkeley National Laboratory; the NCEM is supported by the Director, Office of Basic Energy Sciences, Materials Science Division, US Department of Energy under Contract No. DE-AC03-76SF00098.
|
||||
|
||||
# References
|
||||
|
||||
[1] M.C. Salvadori, Y. Miyao and G. Moscati, Diamond Related Mater., 4 (1995) 1069.
|
||||
[2] A.M. Bonnot, Thin Solid Films, 185 (1990) 111.
|
||||
[3] A. Sawabe and T. Inuzuka, Thin Solid Films, 137 (1986) 89.
|
||||
[4] M.A. Brewer, I.G. Brown, M.R. Dickinson, J.E. Calvin and M.C. Salvadori, Rev. Sci. Instrum., 63 (1992) 3389.
|
||||
[5] K. Suzuki, A. Sawabe, H. Yasuda and T. Inuzuka, Appl. Phys. Lett., 50 (1987) 728.
|
||||
[6] L.M. Hanssen, W.A. Carrington, J.E. Butler and K.A. Snail, Mater. Lett., 7 (1988) 289.
|
||||
[7] M.C. Salvadori, V.P. Mummann, O.G. Martins and F.T. Degasperi, Plasma Sources: Sci. Technol., 4 (1995) 489.
|
||||
[8] W.R. Runyan and K.B. Bean, Semiconductor Integrated Circuit Processing Technology, Addison-Wesley, New York, 1994.
|
||||
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# MULTILAYER DIAMOND HEAT SPREADERS FOR ELECTRONIC POWER DEVICES
|
||||
|
||||
K. JAGANNADHAM
|
||||
|
||||
Materials Science and Engineering, North Carolina State University, Raleigh, NC 27695-7916, U.S.A.
|
||||
|
||||
(Received 3 March 1998; accepted 4 June 1998)
|
||||
|
||||
AbstractÐSingle layer diamond and multilayer diamond heat spreader substrates are prepared and bonded to device wafers of silicon and gallium arsenide. Metallization schemes for the diamond surface and the backside of the device wafers are described. Bonding of the device wafers to the diamond substrates using the high thermal conductivity gold±tin eutectic solder is carried out. Characterization of the bond for the distribution of dierent elements in the metallization layers and the solder, for the presence of microscopic defects such as voids and cracks, for the adhesion strength and for the stability of the bond under thermal cycling is performed. The heat spreader characteristics of the substrates with single and multlayer diamond are determined using infrared imaging of the bonded device wafers and compared with that of wafers bonded to metal substrates. Modeling and analysis of the eective thermal conductivity showed that the multilayer diamond substrates are better heat spreaders and reduce the device temperature so that the life of the electronic devices is prolonged. # 1998 Published by Elsevier Science Ltd. All rights reserved
|
||||
|
||||
# 1. INTRODUCTION
|
||||
|
||||
Heat spreading applications in electronics packaging, hitherto, are handled by high thermal conductivity materials such as beryllium oxide. Recent progress towards microminiaturization and high packaging densities leading to higher density of devices and modules as well as introduction of high frequency and high power devices compounded the problem of heat dissipation. It is realized that more ecient and fast dissipation of heat generated by the devices can only be met by the use of diamond ®lms.
|
||||
|
||||
Power semiconductor devices rely upon the e- cient removal of heat for high frequency switching[1±3]. Natural diamond with high thermal conductivity (20 W/cm K), high electrical resistivity $( 1 0 ^ { 1 6 } \Omega \mathrm { c m } ) ^ { \dag }$ , low dielectric constant (5.7), high dielectric strength (106 V/cm), and matching thermal expansion coecient has been used in bonding devices such as laser diodes[4,5] to dissipate the thermal load. The advent of low pressure synthesis of diamond has helped to replace the high cost natural diamond. It is increasingly realized that the high thermal conductivity of synthetic diamond (10 W/cm K) by itself is not enough to dissipate the heat as the heat capacity of diamond is not large. Therefore, the electronic packaging industry can use the diamond heat spreaders provided the heat is absorbed by a high heat capacity substrate such as molybdenum or silicon nitride which can in turn be cooled by solid, liquid or vapor coolants. The important requirements that should be met before diamond coated heat spreaders can be used
|
||||
|
||||
successfully include good adhesion of diamond to the substrates, stability of the bonded structure to thermal cycling, good heat spreader characteristics of the multilayer bonded structure, reliable process and bonding technology.
|
||||
|
||||
We have developed the multilayer synthetic diamond coating technology on two types of substrates: molybdenum metallic substrate or silicon nitride ceramic substrate. The metallization and bonding procedure that provides reliable bonding to the device wafers such as silicon and gallium arsenide are also established. Characterization of the bonded microstructure, thermal stability and heat spreader properties are presented in the following.
|
||||
|
||||
# 2. EXPERIMENTAL PROCEDURE
|
||||
|
||||
Single layer continuous diamond ®lm of thickness 6 mm or multilayer diamond ®lm of thickness 10 mm was deposited on molybdenum or silicon nitride substrates of thickness 3±4 mm. The diamond layer in these ®lms was deposited by hot ®lament chemical vapor deposition. The details of diamond deposition were described in detail in our earlier work[6,7]. Single layer diamond ®lm deposited on molybdenum for 8 h to achieve a thickness of 10- 14 mm was found to delaminate from the diamond substrate. The large thermal stresses resulting from dierences in thermal expansion coecient between diamond $( \alpha = 3 . 1 \times 1 0 ^ { - 6 } / \mathrm { K } )$ and molybdenum carbide $( \alpha = 5 . 8 \times 1 0 ^ { - 6 } / \mathrm { K } )$ formed on molybdenum $( \alpha = 4 . 9 \times 1 0 ^ { - 6 } / \mathrm { K } )$ substrate were responsible for the delamination. The results of residual stress
|
||||
|
||||
analysis using X-ray diraction and Raman spectroscopy are described more completely in a recent work[7]. The diamond ®lms grown on silicon nitride $( \alpha = 2 . 3 \times 1 0 ^ { - 6 } / \mathrm { K } )$ were not susceptible to delamination as a result of matching thermal expansion coecients[8,9]. The multilayer diamond coated substrates consist of a ®rst discontinuous layer of diamond deposited for 4 h under the same conditions as in the single layer diamond. In order to improve the adhesion of this ®rst layer of discontinuous diamond, an intermediate or second layer consisting of aluminium nitride of 1±2 mm thickness was deposited. The choice of aluminium nitride was based on the reasonably large value of its thermal conductivity (3.7 W/cm K), matching thermal expansion coecient $( 4 . 1 \times 1 0 ^ { - 6 } / \mathrm { K } )$ and high dielectric constant (8.8). In addition, the ease of deposition of high quality aluminium nitride ®lms was a contributing factor. Deposition of aluminium nitride was carried out either by pulsed laser ablation (KrF at 248 nm) or reactive magnetron sputtering[10] with the substrate maintained between 600 and 6508C. The experimental details of deposition of AlN are described in a recent publication[10]. Silicon carbide with a high thermal conductivity $( 5 \mathrm { { W / c m } \mathrm { { K } ) } }$ , matching thermal expansion coecient $( 4 . 3 \times 1 0 ^ { - 6 } / \mathrm { K } )$ and a high dielectric constant (9.0), although a good candidate for the embedding intermediate layer in the composite, cannot be deposited with the same good crystalline quality at these low temperatures. A ®nal layer of continuous diamond was deposited on the top for 6±8 h to provide a total thickness of 10±12 mm of diamond ®lm. Figure 1 shows a schematic illustration of the multilayer diamond ®lm bonded to a device wafer. The multilayer diamond ®lms on both molybdenum and silicon nitride substrates were found to be strongly adherent. Raman spectroscopy was used to characterize single layer and multilayer diamond ®lm and the results showed the characteristic diamond peak with the absence of either graphite or diamondlike phase[6,7]. X-ray diraction was used to determine
|
||||
|
||||
|
||||
Fig. 1. Schematic illustration of the structure of multilayer diamond heat spreader bonded to a device wafer.
|
||||
|
||||
the crystalline quality of the aluminium nitride phase.
|
||||
|
||||
Ecient heat dissipation from the devices was made possible by forming a solid state bond with the diamond substrate. The thermal resistance oered by the bond should be minimized at the same time the strength and thermal stability of the bond should be maintained. In order to enable the bond formation, metallization of diamond ®lm surface was carried out by deposition of titanium, gold and copper layers by laser physical vapor deposition. The multitarget deposition chamber was evacuated to a predeposition vacuum of better than $1 0 ^ { - 7 }$ Torr to prevent titanium oxide formation. Titanium was deposited at a substrate temperature of 6008C initially to prevent diamond decomposition to graphite followed by quickly heating to 7008C. Deposition of gold and copper ®lms was continued while cooling the substrate to room temperature. The thickness of each layer was estimated to be 0.3±0.5 mm. The deposition of copper layer, because of the high re¯ectivity, was carried out for 40 000 pulses to achieve a thickness of 0.5 mm. The choice of titanium to form the carbide with diamond, that of gold to prevent reaction of tin in gold±tin eutectic solder with titanium and that of copper to form a low temperature solid state bond with the solder was also found suitable for relaxation of thermal stresses during thermal cycling of the bond[9,11]. Similarly, the metallization of the backside of silicon wafer of thickness of 500 mm was carried out by deposition of titanium, gold and copper each for 20 000 pulses at room temperature. On the other hand, a dierent scheme for metallization of GaAs wafer was used which consisted of deposition of gold followed by that of Cu±Ge alloy by laser ablation with the wafer substrate maintained at room temperature. This metallization procedure in case of thin GaAs wafer was chosen so that the thermal stresses developed during cooling of the bond are relieved by plastic relaxation and secondly, wetting of the solder with the device wafers is accomplished[6]. The thickness of GaAs wafer was only 100 mm and yet the metallization and bonding procedure was carried out successfully without failure of the thin device wafer.
|
||||
|
||||
The device wafer was bonded to the diamond substrate by heating with the low melting point (2808C) gold±tin eutectic alloy solder ®lm, placed in the middle, to a temperature of 3608C in a hydrogen atmosphere of 5 Torr followed by slow cooling to room temperature after 3 min. Spring loaded setup was used to apply small pressure so that a thin ®lm of the bond was formed. The high thermal conductivity and smaller thickness of the bond were important features that improve the eective thermal conductivity of the diamond heat spreader. Although gold±tin eutectic solder is not very ductile at lower temperatures, as will be seen in the follow-
|
||||
|
||||
ing results, the ability to wet the copper layer helped the bond formation.
|
||||
|
||||
In order to test the eective thermal conductivity and the heat spreader characteristics of the bonded single layer and multilayer diamond substrates, platinum resistance heater was deposited by laser physical vapor deposition on the front side of silicon wafer prior to bonding. Figure 2 is an infrared image of the platinum resistance heater after a constant power input. Calibration of the IR images enabled the temperature changes to be measured with time along the complete wafer for dierent ®xed values of power input into the heater[12].
|
||||
|
||||
# 3. EXPERIMENTAL RESULTS
|
||||
|
||||
The bonded specimens were characterized for adhesion strength, uniformity of composition of the bond, resistance to cracking or delamination under thermal cycling, and heat spreader characteristics or eective thermal conductivity. The strength of the bond was tested using a pull test[6] on a prototype silicon substrate on which diamond ®lm was deposited. The strength of the bond was found to be 5.0 MPa with the delamination taking place along titanium/diamond interface. Formation of titanium carbide is responsible for the adhesion strength of the metallization layers with diamond. Higher substrate temperature for deposition of titanium is expected to improve the formation of higher quality titanium carbide. The distribution of dierent elements present in the bonded wafers was determined by X-ray analysis and mapping of the crosssection samples prepared after thermal cycling. Figure 3 shows the X-ray maps of distribution of Si, Au, Sn, C, Al, Ti and Cu and scanning electron microscopy (SEM) image of a cross-section specimen of silicon wafer bonded to diamond/AlN/diamond/Si3N4 substrate prepared after thermal cycling between 25 and 1508C. The absence of silicon and carbon in the solder region helps to show
|
||||
|
||||
|
||||
Fig. 2. Infrared image of the resistance heater and the device wafer bonded to the diamond heat spreader.
|
||||
|
||||
that diusion of these two elements is con®ned. Diusion of copper into the device wafer is prevented by the presence of gold and titanium layers. Also, the irregular interface between titanium, diamond (carbon) and the substrate seen in the SEM image is an artefact of cutting and irregular features seen on the surface. The signal from diamond was not very strong since carbon is a low atomic number element and in addition, the cross-section specimen was not polished to expose the diamond but more importantly to reveal the presence of voids or cracks in the bonded region that might have formed during thermal cycling. We have not observed the presence of any microscopic defects indicative of failure by cracking or delamination. Figure 4shows the distribution of dierent elements in a cross-section specimen of GaAs wafer bonded to multilayer diamond on molybdenum prepared by angle polishing at 118 to the plane of the bonded interface. As a result the interface region could be seen magni®ed with delineation of dierent regions. Similar to the results shown in Fig. 3, the distribution of dierent elements is con®ned with no interdiusion into the device GaAs wafer. A more important result common to both Figs 3 and 4 is that the metallization layers of titanium, gold and copper are distributed uniformly in the solder region which is expected since the diusion in the liquid phase $( 1 . 0 \times 1 0 ^ { - 4 } \mathrm { c m } ^ { 2 } / \mathrm { s } )$ is much faster and the solder layer is only a few micrometers in thickness.
|
||||
|
||||
Thermal cycling was performed in two temperature ranges on dierent bonded specimens. In the ®rst, each cycle consisted of slow heating to 1508C from room temperature and cooling back in an atmosphere of nitrogen. Another set of specimens were subjected to the second range of thermal cycling wherein the specimens were rapidly heated to 1508C and quenched to ÿ208C in air. The specimens were examined by optical and scanning electron microscopy for delaminated regions either along diamond/substrate interface or diamond/ solder interface and for the presence of cracks in the wafer. The bonded specimens tested by slow cycling were very good without cracking or debonding. However, a small fraction of specimens of silicon wafer bonded to diamond/silicon nitride and subjected to rapid cooling to 208C showed delamination after several cycles. Figure 5 is the cross-section SEM image with X-ray maps of the silicon wafer bonded to diamond on silicon nitride which exhibited upon quenching resistance to delamination. Figure 6, on the other hand, shows the SEM image and X-ray maps of the planar region of the bond that failed by delamination. The interface in Fig. 5 was very good without the presence of any cracks and voids[9]. The distribution of all the elements in the X-ray maps shown in Fig. 6 was uniform and, in particular, there was no segregation that could be responsible for delamination. The high strain rate to which the specimens are sub-
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 3. X-ray mapping of dierent elements and SEM image of the cross-section of silicon wafer bonded to silicon nitride after thermal cycling between 25 and 1508C.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 4. X-ray mapping of dierent elements and SEM image of the cross-section of GaAs wafer bonded to molybdenum after thermal cycling between 25 and 1508C.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 5. X-ray mapping of dierent elements and SEM image of the cross-section of silicon wafer bonded to silicon nitride after rapid thermal cycling between ÿ20 and 1508C.
|
||||
|
||||
jected during quenching may be responsible for failure along voids or cracks that could be present in the solder region. The brittle nature of the solder region may also be a contributing factor. Introduction of excess gold in the eutectic solder is expected to improve the ductility and the toughness of the solder and thereby prevent failure during quenching.
|
||||
|
||||
The temperature raise on the wafer was measured along a line perpendicular to the platinum resistance heater for dierent values of power input. The rate of increase of temperature per unit power input was determined and shown in Fig. 7 for the three types of substrates, namely, bare molybdenum, molybdenum with single layer diamond, and molybdenum with diamond/AlN/diamond. These results clearly show that diamond heat spreaders perform much better than the bare molybdenum heat spreader and in addition, the multilayer diamond is better than the single layer diamond. Thus, AlN embedding layer has improved the eective thermal conductivity of multilayer diamond heat spreader[12].
|
||||
|
||||
# 4. DISCUSSION
|
||||
|
||||
The adhesion strength of the bond is found to be high in the device wafers bonded to diamond on molybdenum or silicon nitride substrates. X-ray maps of dierent elements showed the uniform distribution of dierent elements in the metallization and solder regions. Thus, the wetting reaction of
|
||||
|
||||
solder with the device wafer and the diamond substrate was good without interdiusion of either carbon or silicon in case of silicon wafer and gallium or arsenic in case of GaAs wafer into the solder. Similarly, interdiusion of copper or gold into the device wafers was also absent. Diusion lengths of dierent elements in liquid solder within the bond processing period of 3-5 min is estimated to be 1- 2 mm which is considerably larger than the thickness of solder region. Therefore, the metallization layers and the solder region have become a single region with small gradients in concentration. Titanium carbide present across the interface with diamond provides the adhesion strength of the metallization layer to the substrate. The low conductivity of the metallization layers and that of the carbide layer is partly responsible for reduction of eective thermal conductivity associated with diamond heat spreader. However, the high heat capacity of these layers compensates for the low value of diamond. Thermal stresses in the thin GaAs device wafers should be reduced to prevent failure of the wafer by cracking. The plasticity of the metallization layer of copper±germanium on the backside is found to improve the toughness of the bond and prevent cracking of the thin (100 mm) GaAs wafer. Failure of the silicon wafers bonded to diamond substrate by delamination upon quenching below room temperature may be associated with phase transformation of tin in the tin-rich solder regions around 138C and the accompanying large volume change (27%). Although no detection of
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Fig. 7. Results of infrared imaging of silicon wafers bonded to bare molybdenum, single layer diamond coated molybdenum and multilayer diamond coated molybdenum substrates. Temperature at a ®xed point measured along the line perpendicular to the heater is plotted as a function of time. Average slope corresponds to that for three input power settings. For each substrate, the values of the slope differed only in the ®fth decimal place for the three power input settings[11].
|
||||
|
||||
free tin or segregation of tin is observed in the SEM micrographs of the planar specimens shown in Fig. 6, we believe that there may be small amounts of tin responsible for the large volume change. Also, tin-rich solder may be more sensitive to high strain rates obtained by rapid cooling. We will use solders that are richer in gold to prevent delamination[13].
|
||||
|
||||
The heat spreader characteristics of the multilayer diamond were found to be better than that of single layer diamond. Single layer polycrystalline diamond deposited on any substrate is known to contain microscopic voids and amorphous diamondlike carbon regions between the grain boundaries. These regions of discontinuity in heat transfer reduce the eective thermal conductivity. The eective thermal conductivity of diamond/AlN/diamond has been modeled using the multilayer arrangement shown in Fig. 8 with heat ¯ow in the direction normal to the interface[14]. Three types of interfaces between AlN and diamond are possible. These are a sharp interface, a graded interface and a diused interface. A sharp interface is de®ned by a discontinuous change in thermal conductivity from that of diamond to that of AlN. A graded interface is obtained when the thermal conductivity across the interface changes linearly from that of diamond to that of AlN across a region of width d of the interface. A diused interface, on the other hand, consists of a change in the thermal conductivity from that of diamond to that of AlN but not necessarily linearly and may also have a minimum or a maximum across the interface, as shown in Fig. 8. A graded or diused interface forms when the two adjacent phases interact to form a region of varying compo-
|
||||
|
||||
sition. The presence of a maximum can only be fortuitous and has never been realized. The eective thermal conductivity, $K _ { \mathrm { e f f } } ,$ of this composite region may be obtained from[15]
|
||||
|
||||
$$
|
||||
1 / K _ {\mathrm {e f f}} = V _ {\mathrm {d}} / K _ {\mathrm {d}} + V _ {\mathrm {a}} / K _ {\mathrm {a}} + 2 V _ {\mathrm {i}} / K _ {\mathrm {i}}, \tag {1}
|
||||
$$
|
||||
|
||||
where the subscript d indicates diamond, a represents aluminium nitride, and i represents the interface formed on either side, as shown in Fig. 8. In the above equation the V represents the volume fraction and K the thermal conductivity of each phase and for the model shown in Fig. 8, the volume fraction is proportional to the dimension of each phase in the direction of heat ¯ow. The last term in the above equation can be determined using any variation in the thermal conductivity across the
|
||||
|
||||
|
||||
Fig. 8. Schematic illustration of a diused interface formed between diamond and aluminum nitride. A graded or smooth interface is formed when there is no minimum in the interface. A sharp interface is formed when the interface volume is zero.
|
||||
|
||||
|
||||
Fig. 9. Eective thermal conductivity of the composite structure illustrated in Fig. 8 shown as a function of the volume fraction of the interface. Interfacial thermal resistance for a sharp interface is considered to be zero. Volume fraction of the interface region plus the AlN phase is kept constant at 0.0588.
|
||||
|
||||
interface. Thus for a graded interface, $1 / K _ { \mathrm { i } } { = } 1 /$ $( \alpha d ) \mathrm { l n } ( K _ { \mathrm { d } } / K _ { \mathrm { a } } )$ where $\alpha = ( K _ { \mathrm { d } } { - } K _ { \mathrm { a } } ) / d .$ On the other hand, the equivalent expression for a diused interface takes the form
|
||||
|
||||
$$
|
||||
1 / K _ {\mathrm {i}} = (1 / d \alpha_ {1}) \ln \left(K _ {\mathrm {d}} / K _ {\mathrm {i}}\right) + (1 / d \alpha_ {2}) \ln \left(K _ {\mathrm {i}} / K _ {\mathrm {a}}\right) ], \tag {2}
|
||||
$$
|
||||
|
||||
where $\alpha _ { 1 } = ( K _ { \mathrm { d } } { - } K _ { \mathrm { a } } ) / d _ { 1 } , \alpha _ { 1 } = ( K _ { \mathrm { i } } { - } K _ { \mathrm { a } } ) / d _ { 2 } .$ d1 and d2 are the dimensions of the interfacial regions $( d = d _ { 1 } + d _ { 2 } )$ , with changes in thermal conductivity, as shown in Fig. 8. For a sharp interface, $V _ { \mathrm { i } } { = } 0$ but an interfacial thermal barrier resistance can be de®ned in the form $2 V _ { \mathrm { i } } / K _ { \mathrm { i } } { = } 2 V _ { \mathrm { a } } / d h _ { \mathrm { c } }$ . The eective thermal conductivity in the presence of a sharp interface is controlled by the non-dimensionless parameter, $K _ { \mathrm { a } } / d h _ { \mathrm { c } }$ . When $K _ { \mathrm { a } } / d h _ { \mathrm { c } }$ becomes in®nitely large $( h _ { \mathrm { c } } { = } 0 )$ , the eective thermal conductivity corresponds to the value for polycrystalline diamond with a dispersed void space.
|
||||
|
||||
A detailed numerical analysis of the eective thermal conductivity of the diamond/AlN/diamond composite is presented in Ref.[14] for three dierent situations, namely, when the interfacial layer is formed in the AlN region or in the diamond region or in both the AlN and diamond regions equally. The results of analysis when the diused interface is formed in the AlN region are presented in Fig. 9. The eective thermal conductivity of the composite is seen to increase with increase in volume fraction of the interfacial region although a minimum is present in the thermal conductivity across the interface. The diamond layer of thickness 4 mm on either side surrounds the AlN region of 0.5 mm with the thickness of interface region increase and that of AlN decrease for larger volume fraction of the interface. The thermal conductivity of diamond was assumed to be 20 W/cm K and that of AlN at 3.7 W/cm K with the minimum value of the thermal conductivity across the interface chosen to be 1.0 W/cm K. It is seen that the composite with the graded interface has the highest thermal conductivity with that of diused interface at the intermediate value and that
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|
||||
with sharp interface lowest when the interfacial thermal resistance was zero. If the interfacial thermal resistance were to be very high as in the case of diamond ®lm with voids across the interface, the eective thermal conductivity of the composite with sharp interface will be very small. We have not assumed this situation since percolation paths are also available for heat ¯ow. These results shown in Fig. 9 illustrate that the eective thermal conductivity of diamond/AlN/diamond composites will be higher than that of polycrystalline synthetic diamond with diamondlike carbon or voids.
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# 5. CONCLUSIONS
|
||||
|
||||
Diamond heat spreaders were successfully bonded to device wafers of either silicon or GaAs using gold±tin eutectic solder with proper metallization procedures. AlN embedding layer improves the adhesion strength of diamond to molybdenum or silicon nitride, thermal stability of the bond and the heat spreader characteristics. In the present study, we have shown that multilayer diamond ®lms exhibit higher eective thermal conductivity than either single layer diamond or molybdenum. Modeling and analysis of the interface region suggests that AlN ®lm replaces the diamondlike carbon phase and void space between large grains of diamond and thereby volume fraction of higher conductivity region is improved in multilayer diamond composites. Further, we have shown that the multilayer diamond heat spreaders are helpful to lower the temperature of the electronic devices and thereby prolong their life.
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AcknowledgementsÐThis research is supported by the Division of DMII, NSF. Also, this research is sponsored by SURA and the Assistant Secretary for Energy Eciency and Renewable Energy, Oce of Transportation Technologies, as part of the HTML User Program, ORNL, managed by Lockheed Martin Energy Research Corp. for the U.S. DOE under contract number DE-AC05-96OR22464.
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# REFERENCES
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||||
1. Kuttel, O. M., Schaller, E., Osterwalder, J. and Schlapbach, L., Diamond Related Mater., 1995, 4, 612.
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2. Boudreaux, P. J., Applications of diamond ®lms and related materials: 3rd Int. Conf., ed. A. Feldman et al. NIST Special Publication 885, Washington, DC, 1995.
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3. Ashley, S., Mech. Eng., 1990, 112, 54.
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4. Behr, W. and Luy, J. F., IEEE Electron Device Lett., 1990, 11, 206.
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5. Ukita, H., Nakada, H. and Abe, T., Jpn. J. Appl. Phys., 1992, 31, 524.
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6. Fan, W. D., Jagannadham, K. and Narayan, J., Proc. MRS Symposium, Vol. 416. Boston, MA, 1995.
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7. Jagannadham, K., Watkins, T. R. and Narayan, J., Proc. MRS Symposium, Vol. 458. Boston, MA, 1996.
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8. Touloukin, Y. S., Kirby, R. K., Taylor, R. E. and Lee, T. Y. R. (Eds), Thermal expansion (nonmetallic solid). IFI Plenum, New York, 1977.
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9. Ramaswamy, B. and Jagannadham, K., Proc. MRS Symposium. Boston, MA, 1997.
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10. Jagannadham, K., Sharma, A. K., Wei, Q., Kalayanaraman, R. and Narayan, J., J. Vac. Sci. Tech. Submitted.
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11. Katz, A., Balocchi, F., Lane, E., Lee, C. H., Hall, C., Doting, J., Grijsbach, C. and Harris, K., J. Appl. Phys., 1994, 75, 563.
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12. Jagannadham, K., Dinwiddie, R. B. and Narayan, J., Proc. MRS Symp., Vol. 445. Boston, MA, 1996.
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13. Yost, F. G., Karnowsky, M. M., Drotning, W. D. and Gieske, J. H., Met. Trans. A, 1990, 21, 1885.
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14. Jagannadham, K., J. Appl. Phys. Submitted.
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15. Hasselman, D. P. and Johnson, L. F., J. Compos. Mater., 1987, 21, 508.
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